MAX1109EUB Maxim Integrated, MAX1109EUB Datasheet - Page 14

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MAX1109EUB

Manufacturer Part Number
MAX1109EUB
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX1109EUB

Number Of Channels
2
Architecture
SAR
Conversion Rate
50 KSPS
Resolution
8 bit
Input Type
Single-Ended/Pseudo-Differential
Snr
Yes
Interface Type
4-Wire (SPI, Microwire), QSPI
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
uMAX-10
Maximum Power Dissipation
444 mW
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
4.096 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MAX1109EUB+
Manufacturer:
Maxim
Quantity:
500
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
initiated. The MSB successive-approximation bit deci-
sion is made on the rising edge of the seventh SCLK.
On the falling edge of the eighth SCLK, the MSB is
clocked out on the DOUT pin; on each of the next
seven SCLK falling edges, the remaining bits of conver-
sion are clocked out. Zeros are clocked out on DOUT
after the LSB has been clocked out, until CS is dis-
abled. Then DOUT becomes high impedance and the
part is ready for another conversion (Figure 6).
The conversion must complete in 1ms, or droop on the
sample-and-hold capacitors may degrade conversion
results. Use internal clock mode if the serial-clock fre-
quency is less than 50kHz, or if serial-clock interruptions
could cause the conversion interval to exceed 1ms.
Figure 6. Single Conversion Timing, External Clock Mode
Figure 7. Detailed Serial-Interface Timing
14
DOUT
A/D STATE
SCLK
DIN
CS
______________________________________________________________________________________
SCLK
DOUT
DIN
CS
START
MSB
t
1
CSH
SEL2
IDLE
SEL1
t
t
DV
CSS
t
DS
SEL0
t
DH
4
I/ECLK I/EREF
t
ACQ
t
CL
SHDN
REF
SHDN
LSB
t
8
CH
MSB
D7
D6
Internal clock mode frees the µP from the burden of
running the SAR conversion clock. This allows the con-
version results to be read back at the processor’s con-
venience, at any clock rate up to 2MHz.
An internal register stores data when the conversion is
in progress. On the falling edge of the fourth SCLK,
track mode is enabled, and on the falling edge of the
eighth SCLK, acquisition is complete and internal con-
version is initiated. The internal 400kHz clock com-
pletes the conversion in 20µs typically (35µs max), at
which time the MSB of the conversion is present at the
DOUT pin. The falling edge of SCLK clocks the remain-
ing data out of this register at any time after the conver-
sion is complete (Figure 8).
D5
t
CONV
D4
12
D3
t
DO
D2
D1
LSB
D0
16
t
CSH
IDLE
t
TR
Internal Clock
20

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