C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 396
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C8051F960-A-GQ
Manufacturer Part Number
C8051F960-A-GQ
Description
8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F960-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Available stocks
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C8051F960-A-GQ
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C8051F96x
28.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. If hardware ACK generation
is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The
software must respond to the received slave address with an ACK, or ignore the received slave address
with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address
which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK
cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are trans-
mitted. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmit-
ted. The interface enters Slave Transmitter Mode, and transmits one or more bytes of data. After each byte
is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should
be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to
before SI is cleared (an error condition may be generated if SMB0DAT is written following a received
NACK while in Slave Transmitter Mode). The interface exits Slave Transmitter Mode after receiving a
STOP. Note that the interface will switch to Slave Receiver Mode if SMB0DAT is not written following a
Slave Transmitter interrupt. Figure 28.8 shows a typical slave read sequence. Two transmitted data bytes
are shown, though any number of bytes may be transmitted. All of the “data byte transferred” interrupts
occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is enabled.
396
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 28.7. Typical Slave Write Sequence
W
A
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
Data Byte
Rev. 0.5
A
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Data Byte
A
P
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