GTL2003BQ,115 NXP Semiconductors, GTL2003BQ,115 Datasheet
GTL2003BQ,115
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GTL2003BQ,115 Summary of contents
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GTL2003 8-bit bidirectional low voltage translator Rev. 01 — 27 July 2007 1. General description The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2003 provides 8 ...
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... NXP Semiconductors 3. Applications I Any application that requires bidirectional or unidirectional voltage level translation from any voltage from 1 5 any voltage from 1 5 The open-drain construction with no direction pin is ideal for bidirectional low voltage (for example, 1.0 V, 1 1.8 V) processor I normal 3.3 V and/or 5 signal levels ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning GND SREF Fig 2. Pin configuration for TSSOP20 6.2 Pin description Table 3. Symbol GND SREF DREF GREF [1] DHVQFN package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board ...
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... NXP Semiconductors 7. Functional description Refer also to 7.1 Function selection Table 4. Assumes the higher voltage level HIGH voltage level LOW voltage level Don’t care [1] GREF [1] GREF should be at least 1.5 V higher than SREF for best translator operation. [ equal to the SREF voltage. ...
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... NXP Semiconductors 8. Application design-in information 8.1 Bidirectional translation For the bidirectional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the GREF input must be connected to DREF and both pins pulled to HIGH side V DREF is recommended. The processor output can be totem pole or open-drain (pull-up ...
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... NXP Semiconductors 8.2 Unidirectional down translation For unidirectional clamping, higher voltage to lower voltage, the GREF input must be connected to DREF and both pins pulled to the higher side V (typically 200 filter capacitor on DREF is recommended. Pull-up resistors are required if the chip set I/O are open-drain. The opposite side of the reference transistor (SREF) is connected to the processor core supply voltage ...
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... NXP Semiconductors 8.4 Sizing pull-up resistor The pull-up resistor value needs to limit the current through the pass transistor when the ‘on’ state to about 15 mA. This will guarantee a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage will also be higher in the ‘ ...
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... NXP Semiconductors 9. Limiting values Table 7. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V SREF V DREF V GREF stg [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C ...
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... NXP Semiconductors 11. Static characteristics Table 9. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V LOW-level output voltage OL V input clamping voltage IK I gate input leakage current LI(G) C input capacitance at gate ig C off-state input/output io(off) capacitance C on-state input/output io(on) capacitance R ON-state resistance ...
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... NXP Semiconductors 12. Dynamic characteristics 12.1 Dynamic characteristics for translator-type application Table 10 + amb GND = Symbol t PLH t PHL [1] All typical values are measured at V [2] Propagation delay is measured using and is guaranteed by ON-state resistance. [3] C io(on) Fig 7. The input (Sn) to output (Dn) propagation delays GTL2003_1 Product data sheet Dynamic characteristics = 1.365 V to 1.635 V ...
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... NXP Semiconductors 12.2 Dynamic characteristics for CBT-type application Table 11 + amb Refer to Figure Symbol t PD [1] This parameter is warranted by the ON-state resistance, but is not production tested. The propagation delay is based on the RC time constant of the typical ON-state resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance). ...
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... NXP Semiconductors 13. Test information Fig 9. Load circuit for translator-type applications Fig 10. Load circuit for CBT-type application Table 12. Test PLZ PZL PHZ PZH GTL2003_1 Product data sheet V V DD1 DD2 200 k DREF GREF SREF V ref pulse generator from output under test Test data are given in Table 12 ...
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... NXP Semiconductors 14. Package outline TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 13. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 16. Abbreviations Table 15. Acronym CDM CMOS DUT ESD GTL HBM 2 I C-bus LVTTL MM NMOS TTL TVC 17 ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 7.1 Function selection Application design-in information . . . . . . . . . . 5 8.1 Bidirectional translation 8.2 Unidirectional down translation ...