GTL2012DP,118 NXP Semiconductors, GTL2012DP,118 Datasheet
GTL2012DP,118
Specifications of GTL2012DP,118
935283869118
GTL2012DP-T
Related parts for GTL2012DP,118
GTL2012DP,118 Summary of contents
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GTL2012 2-bit LVTTL to GTL transceiver Rev. 01 — 9 August 2007 1. General description The GTL2012 is a 2-bit translating transceiver designed for 3.3 V system interface with a GTL /GTL/GTL+ bus. The direction pin (DIR) allows the part ...
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... NXP Semiconductors 4. Ordering information Table 2. Ordering information +85 C amb Type number Topside mark GTL2012DP 012P GTL2012DC 012C [1] Also known as MSOP8. 5. Functional diagram Fig 1. Logic diagram of GTL2012 GTL2012_1 Product data sheet Package Name Description [1] TSSOP8 plastic thin shrink small outline package; 8 leads; ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning GND Fig 2. Pin configuration for TSSOP8 6.2 Pin description Table 3. Symbol A0 A1 DIR GND B1 B0 VREF Functional description Refer to 7.1 Function table Table HIGH voltage level LOW voltage level. Input DIR H L GTL2012_1 Product data sheet ...
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... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I LOW-level output current ...
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... NXP Semiconductors Table 6. Recommended operating conditions Unused inputs must be held HIGH or LOW to prevent them from floating. Symbol Parameter I LOW-level output current OL T ambient temperature amb [1] Unused inputs must be held HIGH or LOW to prevent them from floating. [2] V maximum of 3.6 V with resistor sized so I ...
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... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics V = 3 Symbol Parameter GTL ; 0.9 V ref TT t LOW-to-HIGH propagation delay PLH t HIGH-to-LOW propagation delay PHL t LOW-to-HIGH propagation delay PLH t HIGH-to-LOW propagation delay PHL GTL 0 1.2 V ref TT t LOW-to-HIGH propagation delay PLH t HIGH-to-LOW propagation delay ...
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... NXP Semiconductors Fig 5. Propagation delay 12. Test information Fig 6. Load circuitry for switching times Fig 7. Load circuit for B outputs R — Load resistor — Load capacitance; includes jig and probe capacitance — Termination resistance; should be equal GTL2012_1 Product data sheet input V ref t PLH ...
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... NXP Semiconductors 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 10. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 11. Acronym CDM CMOS DUT ESD GTL HBM LVTTL MM PRR TTL 16. Revision history Table 12 ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 ...