MCF52236AF50A Freescale Semiconductor, MCF52236AF50A Datasheet - Page 23

• Manufacturer Part Number: MCF52236AF50A
• Description: 32-bit Microcontrollers - MCU KIRIN2E EPP - REVA
• Manufacturer: Freescale Semiconductor

Specifications of MCF52236AF50A

• Core: ColdFire V2
• Processor Series: MCF52235
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: 0 C to + 70 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 8
• Interface Type: I2C, QSPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 56
• Number Of Timers: 4
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

1.7
Table 8
1.8
Table 9
Freescale Semiconductor
Synchronous Peripheral
Twisted Pair Output +
Bias Control Resistor
Twisted Pair Output -
Twisted Pair Input +
QSPI Synchronous
QSPI Synchronous
Twisted Pair Input -
QSPI Serial Clock
describes QSPI signals.
Serial Data Input
describes the Fast Ethernet Controller (FEC) signals.
Signal Name
Signal Name
Collision LED
Transmit LED
Serial Output
Receive LED
Chip Selects
Activity LED
Duplex LED
Speed LED
Queued Serial Peripheral Interface (QSPI)
Fast Ethernet Controller EPHY Signals
Link LED
Table 8. Queued Serial Peripheral Interface (QSPI) Signals
QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active
Abbreviation
Abbreviation
QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be
QSPI_CLK
QSPI_DIN
LINK_LED
SPD_LED
ACT_LED
DUPLED
COLLED
RXLED
TXLED
RBIAS
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
RXP
RXN
TXN
TXP
Table 9. Fast Ethernet Controller (FEC) Signals
driven on the rising or falling edge of QSPI_CLK.
Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK.
Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable.
high or low.
Differential Ethernet twisted-pair input pin. This pin is high-impedance
out of reset.
Differential Ethernet twisted-pair input pin. This pin is high-impedance
out of reset.
Differential Ethernet twisted-pair output pin. This pin is
high-impedance out of reset.
Differential Ethernet twisted-pair output pin. This pin is
high-impedance out of reset.
Connect a 12.4 k(1.0%) external resistor, RBIAS, between the
PHY_RBIAS pin and analog ground.
Place this resistor as near to the chip pin as possible. Stray
capacitance must be kept to less than 10 pF
(>50 pF causes instability). No high-speed signals can be permitted in
the region of RBIAS.
Indicates when the EPHY is transmitting or receiving
Indicates when the EPHY has a valid link
Indicates the speed of the EPHY connection
Indicates the duplex (full or half) of the EPHY connection
Indicates if the EPHY detects a collision
Indicates if the EPHY is transmitting
Indicates if the EPHY is receiving
Function
Function
MCF52235 Family Configurations
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
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