SIM3L144-C-GM Silicon Labs, SIM3L144-C-GM Datasheet - Page 5

• Manufacturer Part Number: SIM3L144-C-GM
• Description: ARM Microcontrollers - MCU 64KB, DC-DC, AES QFN40
• Manufacturer: Silicon Labs

Specifications of SIM3L144-C-GM

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SiM3L1xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-40
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 20
• Interface Type: I2C, SPI
• Length: 4.65 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 28
• Number Of Timers: 3
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.8 V
• Supply Voltage - Min: 1.8 V

SiM3L1xx
1. Related Documents and Conventions
1.1. Related Documents
This data sheet accompanies several documents to provide the complete description of the SiM3L1xx devices.
1.1.1. SiM3L1xx Reference Manual
The Silicon Laboratories SiM3L1xx Reference Manual provides the detailed description for each peripheral on the
SiM3L1xx devices.
1.1.2. Hardware Access Layer (HAL) API Description
The Silicon Laboratories Hardware Access Layer (HAL) API provides C-language functions to modify and read
each bit in the SiM3L1xx devices. This description can be found in the SiM3xxxx HAL API Reference Manual.
1.1.3. ARM Cortex-M3 Reference Manual
The ARM-specific features like the Nested Vectored Interrupt Controller are described in the ARM Cortex-M3
reference documentation. The online reference manual can be found here:
http://infocenter.arm.com/help/topic/com.arm.doc.subset.cortexm.m3/index.html#cortexm3.
1.2. Conventions
The block diagrams in this document use the following formatting conventions:
Internal Module
Other Internal
External Memory
Peripheral Block
Block
DMA Block
Memory Block
External to MCU
Block
Input_Pin
Output_Pin
Functional Block
Internal_Input_Signal
Internal_Output_Signal
REGn_NAME / BIT_NAME
Figure 1.1. Block Diagram Conventions
Rev 0.5
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