MK20DN128VLF5 Freescale Semiconductor, MK20DN128VLF5 Datasheet - Page 46

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MK20DN128VLF5

Manufacturer Part Number
MK20DN128VLF5
Description
ARM Microcontrollers - MCU KINETIS 128K
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK20DN128VLF5

Rohs
yes
Core
ARM Cortex M4
Processor Series
K20
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
128 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MK20DN128VLF5
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Peripheral operating requirements and behaviors
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I
6.8.4 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
46
Symbol
C
ESR
I
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
LIM
OUT
External output capacitor
External output capacitor equivalent series
resistance
Short circuit current
Description
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn invalid delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Table 32. Master mode DSPI timing (limited voltage range)
Table 31. USB VREG electrical specifications
Description
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
(continued)
1.76
Min.
1
(t
(t
(t
SCK
BUS
BUS
2 x t
Min.
2.7
14
/2) − 2
2
2
0
0
x 2) −
x 2) −
BUS
Typ.
290
2.2
1
(t
SCK
Max.
3.6
25
/2) + 2
8
Max.
8.16
100
Freescale Semiconductor, Inc.
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
Unit
mA
μF
Notes
Load
Notes
1
2
.

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