SiM3C157-B-GM Silicon Labs, SiM3C157-B-GM Datasheet - Page 45

• Manufacturer Part Number: SiM3C157-B-GM
• Description: ARM Microcontrollers - MCU 128KB LGA92
• Manufacturer: Silicon Labs

Specifications of SiM3C157-B-GM

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SIM3C1xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 80 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 42 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LGA-92
• Mounting Style: SMD/SMT
• Interface Type: 2 x I2C, I2S, 3 x SPI, 2 x USART, 2 x UART
• Number Of Programmable I/os: 75
• Number Of Timers: 12 x 32 bit
• Supply Voltage - Max: 3.6 V

4.7. Analog
4.7.1. 12-Bit Analog-to-Digital Converters (SARADC0, SARADC1)
The SARADC0 and SARADC1 modules on SiM3C1xx devices are Successive Approximation Register (SAR)
Analog to Digital Converters (ADCs). The key features of the SARADC module are:
4.7.2. Sample Sync Generator (SSG0)
The SSG module includes a phase counter and a pulse generator. The phase counter is a 4-bit free-running
counter clocked from the SARADC module clock. Counting-up from zero, the phase counter marks sixteen equally-
spaced events for any number of SARADC modules. The ADCs can use this phase counter to start a conversion.
The programmable pulse generator creates a 50% duty cycle pulse with a period of 16 phase counter ticks. Up to
four programmable outputs available to external devices can be driven by the pulse generator with programmable
polarity and a defined output setting when the pulse generator is stopped.
The Sample Sync Generator module has the following features:
4.7.3. 10-Bit Digital-to-Analog Converter (IDAC0, IDAC1)
The IDAC takes a digital value as an input and outputs a proportional constant current on a pin. The IDAC module
includes the following features:
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Conversion complete, multiple conversion complete, and FIFO overflow and underflow flags and interrupts
Support for multiple data packing formats, including: single 10-bit sample per word, dual 10-bit samples per
Single-ended 12-bit and 10-bit modes.
Supports an output update rate of 250 k samples per second in 12-bit mode or 1 M samples per second in
10-bit mode.
Operation in low power modes at lower conversion speeds.
Selectable asynchronous hardware conversion trigger with hardware channel select.
Output data window comparator allows automatic range checking.
Support for Burst Mode, which produces one set of accumulated data per conversion-start trigger with
programmable power-on settling and tracking time.
supported.
Flexible output data formatting.
Sequencer allows up to 8 sources to be automatically scanned using one of four channel characteristic
profiles without software intervention.
Eight-word conversion data FIFO for DMA operations.
Multiple SARADC modules can work together synchronously or by interleaving samples.
Includes two internal references (1.65 V fast-settling, 1.2/2.4 V precision), support for an external
reference, and support for an external signal ground.
Connects multiple modules together to perform synchronized actions.
Outputs a clock synchronized to the internal sampling clock used by any number of SARADC modules to
pins for use by external devices.
Includes a phase counter, pulse generator, and up to four programmable outputs.
10-bit current DAC with support for four timer, up to seven external I/O, on demand, and SSG0 output
update triggers.
Ability to update on rising, falling, or both edges for any of the external I/O trigger sources (DACnTx).
Supports an output update rate greater than 600 k samples per second.
Support for three full-scale output modes: 0.5 mA, 1.0 mA and 2.0 mA.
Four-word FIFO to aid with high-speed waveform generation or DMA interactions.
Individual FIFO overrun, underrun, and went-empty interrupt status sources.
word, or four 8-bit samples per word.
Support for left- and right-justified data.
Rev.1.0
SiM3C1xx
45