LPC11E12FBD48/201, NXP Semiconductors, LPC11E12FBD48/201, Datasheet - Page 17

• Manufacturer Part Number: LPC11E12FBD48/201,
• Description: ARM Microcontrollers - MCU 16kB 1kB EE 6kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC11E12FBD48/201,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11E1x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 1 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 250

NXP Semiconductors
LPC11E1X
Product data sheet
7.10.1 Features
7.8.1 Features
7.9.1 Features
7.10 SSP serial I/O controller
7.9 USART
The LPC11E1x contain one USART.
The USART includes full modem control, support for synchronous mode, and a smart
card interface. The RS-485/9-bit mode allows both software address detection and
automatic address detection using 9-bit mode.
The USART uses a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
The SSP controllers operate on a SSP, 4-wire SSI, or Microwire bus. It can interact with
multiple masters and slaves on the bus. Only a single master and a single slave can
communicate on the bus during a given data transfer. The SSP supports full duplex
transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and
from the slave to the master. In practice, often only one of these data flows carries
meaningful data.
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GPIO pins can be configured as input or output by software.
All GPIO pins default to inputs with interrupt disabled at reset.
Pin registers allow pins to be sensed and set individually.
Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request.
Any pin or pins in each port can trigger a port interrupt.
Maximum USART data bit rate of 3.125 Mbit/s.
16 byte receive and transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
Support for RS-485/9-bit mode.
Support for modem control.
Support for synchronous mode.
Includes smart card interface.
Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 February 2012
32-bit ARM Cortex-M0 microcontroller
LPC11E1x
© NXP B.V. 2012. All rights reserved.
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