LPC11E14FHN33/401, NXP Semiconductors, LPC11E14FHN33/401, Datasheet - Page 19

• Manufacturer Part Number: LPC11E14FHN33/401,
• Description: ARM Microcontrollers - MCU 32kB 4kB EE 10kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC11E14FHN33/401,

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC11E1x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
LPC11E1X
Product data sheet
7.13.1 Features
7.15.1 Features
7.13 General purpose external event counter/timers
7.14 System tick timer
7.15 Windowed WatchDog Timer (WWDT)
The LPC11E1x include two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
The purpose of the WWDT is to prevent an unresponsive system state. If software fails to
update the watchdog within a programmable time window, the watchdog resets the
microcontroller
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Optional conversion on transition of input pin or timer match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
Counter or timer operation.
Up to two capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event can also generate an interrupt.
Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
The timer and prescaler can be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
Internally resets chip if not periodically reloaded during the programmable time-out
period.
Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 February 2012
32-bit ARM Cortex-M0 microcontroller
LPC11E1x
© NXP B.V. 2012. All rights reserved.
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