LPC11U34FBD48/421, NXP Semiconductors, LPC11U34FBD48/421, Datasheet - Page 47
LPC11U34FBD48/421,
Manufacturer Part Number
LPC11U34FBD48/421,
Description
ARM Microcontrollers - MCU 32-bit ARM Cortex-M0 48KB Flash 10KB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC11U35FHI33501.pdf
(70 pages)
Specifications of LPC11U34FBD48/421,
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC11U3x
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
48 KB
Data Ram Size
10 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
Factory Pack Quantity
250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC11U34FBD48/421,
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
Table 15.
T
[1]
[5]
[6]
LPC11U3X
Product data sheet
[2]
[3]
[4]
Symbol
f
t
t
t
t
t
SCL
f
LOW
HIGH
HD;DAT
SU;DAT
amb
See the I
Parameters are valid over operating temperature range unless otherwise specified.
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V
bridge the undefined region of the falling edge of SCL.
C
The maximum t
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified t
=
b
−
= total capacitance of one bus line in pF.
40
°
Dynamic characteristic: I
C to +85
2
C-bus specification UM10204 for details.
10.4 I/O pins
10.5 I
Parameter
SCL clock
frequency
fall time
LOW period of the
SCL clock
HIGH period of the
SCL clock
data hold time
data set-up time
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
°
C.
[2]
[2]
[3]
Table 14.
T
[1]
Symbol
t
t
2
amb
r
f
C-bus
The typical frequency spread over processing and temperature (T
See the LPC11Uxx user manual.
Applies to standard port pins and RESET pin.
=
−
40
°
Dynamic characteristics: I/O pins
Parameter
rise time
fall time
C to +85
[4][5][6][7]
[3][4][8]
[9][10]
2
C-bus pins
All information provided in this document is subject to legal disclaimers.
f
.
°
C; 3.0 V
Conditions
Standard-mode
Fast-mode
Fast-mode Plus
of both SDA and SCL
signals
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
[1]
Conditions
pin configured as output
pin configured as output
Rev. 1 — 20 April 2012
Standard-mode
Fast-mode
Fast-mode Plus
≤
V
DD
≤
3.6 V.
[1]
Min
0
0
0
-
20 + 0.1 × C
-
4.7
1.3
0.5
4.0
0.6
0.26
0
0
0
250
100
50
32-bit ARM Cortex-M0 microcontroller
3.0
2.5
Min
amb
b
= −40 °C to +85 °C) is ±40 %.
Typ
-
-
IH
(min) of the SCL signal) to
100
120
-
-
-
-
-
-
Max
400
1
300
300
-
-
-
-
-
-
LPC11U3x
© NXP B.V. 2012. All rights reserved.
Max
5.0
5.0
f
is specified at
Unit
kHz
kHz
MHz
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
47 of 70
Unit
ns
ns