MPC8308ZQAFDA Freescale Semiconductor, MPC8308ZQAFDA Datasheet - Page 71
MPC8308ZQAFDA
Manufacturer Part Number
MPC8308ZQAFDA
Description
Microprocessors - MPU E300 MP Pb 333
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8308VMAGDA.pdf
(83 pages)
Specifications of MPC8308ZQAFDA
Processor Series
MPC8308
Core
e300
Maximum Clock Frequency
333 MHz
Interface Type
I2C, JTAG, UART
Operating Supply Voltage
0.95 V to 1.05 V
Maximum Operating Temperature
0 C to + 105 C
Mounting Style
SMD/SMT
Package / Case
MAPBGA-473
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21 Clocking
This figure shows the internal distribution of clocks within the device.
1
2
The following external clock sources are utilized on the MPC8308:
All clock inputs can be supplied using an external canned oscillator, a clock generation chip, or some other
source that provides a standard CMOS square wave input.
Freescale Semiconductor
Multiplication factor M = 1, 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL].
Multiplication factor L = 2, 3, 4, 5 and 6. Value is decided by RCWLR[SPMF].
•
•
•
•
SYS_CLK_IN
24–66 MHz
SD_REF_CLK_B
SD_REF_CLK
125/100 MHz
System clock (SYS_CLK_IN)
Ethernet Clock (TSEC1_RX_CLK/TSEC1_TX_CLK/TSEC1_GTX_CLK125 for eTSEC)
SerDes PHY clock
eSHDC clock (SD_CLK)
For more information, see the SerDes chapter in the MPC8308 PowerQUICC II Pro Processor
Reference Manual.
SD_CLK
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
+
-
eSHDC
PLL
MPC8308
Figure 53. MPC8308 Clock Subsystem
PCVTR Mux
SerDes PHY
PCI Express
Converter
Protocol
x L
ref
System
PLL
2
fb
Gen
Clk
clk tree
x M
1
e300
PLL
e300 Core
ddr_clk
eTSEC1
lbc_clk
csb_clk
DDR
/n
Clock
Divider
LBC
Clock
Divider
/2
MCK[0:2]
TSEC1_TX_CLK/
TSEC1_GTX_CLK125
TSEC1_RX_CLK
MCK[0:2]
Local
Bus
Memory
Device
DDR
Memory
Device
Clocking
71
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