STM32F103VDT6TR STMicroelectronics, STM32F103VDT6TR Datasheet - Page 86

• Manufacturer Part Number: STM32F103VDT6TR
• Description: ARM Microcontrollers - MCU STM32F103 Perf Line M3 384kB 72 MHz MCU
• Manufacturer: STMicroelectronics

Specifications of STM32F103VDT6TR

• Product Category: ARM Microcontrollers - MCU
• Core: ARM Cortex M3
• Data Bus Width: 32 bit

Electrical characteristics
5.3.14
Table 46.
1. FT = Five-volt tolerant. In order to sustain a voltage higher than V
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
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Symbol
V
R
R
C
V
V
I
disabled.
MOS/NMOS contribution
lkg
hys
PU
PD
IH
IO
IL
Standard IO input low
level voltage
IO FT
voltage
Standard IO input high
level voltage
IO FT
voltage
Standard IO Schmitt
trigger voltage
hysteresis
IO FT Schmitt trigger
voltage hysteresis
Input leakage current
Weak pull-up equivalent
resistor
Weak pull-down
equivalent resistor
I/O pin capacitance
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
performed under the conditions summarized in
compliant.
I/O static characteristics
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in
in
(1)
(1)
Figure 44
Parameter
(5)
input low level
input high level
(2)
to the series resistance is minimum
and
(2)
(5)
(4)
Figure 45
V
V
V
V
Standard I/Os
DD
DD
SS
IN
Conditions
V
V
= 5 V,
> 2 V
≤
≤
IN
IN
2 V
V
for 5 V tolerant I/Os.
=
=
IN
V
V
I/O FT
≤
SS
DD
Doc ID 14611 Rev 8
V
DD
(~10% order)
0.41*(V
0.42*(V
5% V
DD
STM32F103xC, STM32F103xD, STM32F103xE
DD
Figure 42
+0.3 the internal pull-up/pull-down resistors must be
DD
–0.3
–0.3
Min
200
30
30
-2 V)+1.3 V
.
-2 V)+1 V
Table
DD
(3)
Table 46
10. All I/Os are CMOS and TTL
and
Typ
Figure 43
40
40
5
are derived from tests
0.32*(V
0.28*(V
for standard I/Os, and
V
DD
DD
DD
Max
5.5
5.2
-2 V)+0.75 V
±1
50
50
-2 V)+0.8 V
3
+0.3
Unit
mV
mV
kΩ
kΩ
µA
pF
V
V
V
V