74LVC1T45GN,132 NXP Semiconductors, 74LVC1T45GN,132 Datasheet - Page 23
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
74LVC1T45GN,132
Manufacturer Part Number
74LVC1T45GN,132
Description
Bus Transceivers Dual supply trans transceiver
Manufacturer
NXP Semiconductors
Datasheet
1.74LVC1T45GN132.pdf
(33 pages)
Specifications of 74LVC1T45GN,132
Rohs
yes
Factory Pack Quantity
5000
NXP Semiconductors
74LVC_LVCH1T45
Product data sheet
14.2 Bidirectional logic level-shifting application
Figure 16
level-shifting application. Since the device does not have an output enable pin, the system
designer should take precautions to avoid bus contention between system-1 and
system-2 when changing directions.
Table 17
system-2 and then from system-2 to system-1.
Table 17.
[1]
State DIR CTRL I/O-1
1
2
3
4
Fig 16. Bidirectional logic level-shifting application
H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
DIR CTRL
V
I/O-1
H
H
L
L
CC1
provides a sequence that illustrates data transmission from system-1 to
Pull-up or pull-down only needed for 74LVC1T45.
shows the 74LVC1T45; 74LVCH1T45 being used in a bidirectional logic
Description bidirectional logic level-shifting application
system-1
PULL-UP/DOWN
All information provided in this document is subject to legal disclaimers.
output
Z
Z
input
Rev. 6 — 6 August 2012
V
CC1
I/O-2
input
Z
Z
output
V
CC(A)
GND
A
74LVC1T45; 74LVCH1T45
1
2
3
Description
system-2 is getting ready to send data to system-1.
I/O-1 and I/O-2 are disabled. The bus-line state
depends on bus hold.
DIR bit is set LOW. I/O-1 and I/O-2 are still disabled.
The bus-line state depends on bus hold.
system-1 data to system-2
system-2 data to system-1
74LVCH1T45
74LVC1T45
Dual supply translating transceiver; 3-state
6
5
4
V
DIR
B
CC(B)
V
PULL-UP/DOWN
CC2
[1]
system-2
© NXP B.V. 2012. All rights reserved.
V
I/O-2
CC2
001aaj995
23 of 33