74LVCH1T45GS,132 NXP Semiconductors, 74LVCH1T45GS,132 Datasheet - Page 24

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74LVCH1T45GS,132

Manufacturer Part Number
74LVCH1T45GS,132
Description
Bus Transceivers 3.6V 250mW 8.2ns
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVCH1T45GS,132

Rohs
yes
Propagation Delay Time
8.2 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
1.2 V
Maximum Operating Temperature
+ 125 C
Package / Case
XSON-6
Maximum Power Dissipation
250 mW
Mounting Style
SMD/SMT
Factory Pack Quantity
5000
NXP Semiconductors
74LVC_LVCH1T45
Product data sheet
14.3 Power-up considerations
14.4 Enable times
The device is designed such that no special power-up sequence is required other than
GND being applied first.
Table 18.
Calculate the enable times for the 74LVC1T45; 74LVCH1T45 using the following
formulas:
In a bidirectional application, these enable times provide the maximum delay from the
time the DIR bit is switched until an output is expected. For example, if the 74LVC1T45;
74LVCH1T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of
the device must be disabled before presenting it with an input. After the B port has been
disabled, an input signal applied to it appears on the corresponding A port after the
specified propagation delay.
V
0 V
1.8 V
2.5 V
3.3 V
5.0 V
CC(A)
t
t
t
t
PZH
PZL
PZH
PZL
(DIR to A) = t
(DIR to B) = t
(DIR to A) = t
(DIR to B) = t
Typical total supply current (I
V
0 V
0
< 1
< 1
< 1
< 1
CC(B)
All information provided in this document is subject to legal disclaimers.
PHZ
PHZ
PLZ
PLZ
Rev. 6 — 6 August 2012
(DIR to B) + t
(DIR to B) + t
(DIR to A) + t
(DIR to A) + t
1.8 V
< 1
< 2
< 2
< 2
2
74LVC1T45; 74LVCH1T45
2.5 V
< 1
< 2
< 2
< 2
< 2
CC(A)
PLH
PHL
PLH
PHL
(B to A)
(B to A)
(A to B)
(A to B)
Dual supply translating transceiver; 3-state
+ I
CC(B)
)
3.3 V
< 1
< 2
< 2
< 2
< 2
5.0 V
< 1
2
< 2
< 2
< 2
© NXP B.V. 2012. All rights reserved.
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