MAX5705AAUB+ Maxim Integrated, MAX5705AAUB+ Datasheet - Page 23

• Manufacturer Part Number: MAX5705AAUB+
• Description: Digital to Analog Converters - DAC 12Bit 1Ch V Buffered Precision DAC
• Manufacturer: Maxim Integrated

Specifications of MAX5705AAUB+

• Rohs: yes
• Number Of Converters: 1
• Number Of Dac Outputs: 1
• Resolution: 12 bit
• Interface Type: Serial SPI
• Settling Time: 6 us
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX-10
• Maximum Power Dissipation: 707.3 mW
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage Buffered
• Supply Current: 155 uA
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

The RETURN command (B[23:20] = 0111) updates the
RETURN register content for the DAC. If the DEFAULT
configuration register is set to RETURN mode, the DAC
will be cleared or gated to the RETURN register value in
the event of a SW or HW CLEAR or GATE condition. It is
not necessary to program this register if the DEFAULT =
RETURN mode will not be used. The data format for the
RETURN register is identical to that used for CODE and
LOAD operations. See
When power is applied to V
set to zero scale. To optimize DAC linearity, wait until
the supplies have settled and the internal setup and
calibration sequence completes (200Fs, typ).
Bypass V
a low-impedance ground as close as possible to the
device. Minimize lead lengths to reduce lead inductance.
Connect GND to the analog ground plane.
Digital and AC transient signals on GND can create noise
at the output. Connect GND to form the star ground for
the DAC system. Refer remote DAC loads to this system
ground for the best possible performance. Use proper
grounding techniques, such as a multilayer board with
a low-inductance ground plane, or star connect all
ground return paths back to the MAX5703/MAX5704/
MAX5705 GND. Carefully layout the traces between
channels to reduce AC cross-coupling. Do not use wire-
wrapped boards and sockets. Use shielding to maximize
noise immunity. Do not run analog and digital signals
parallel to one another, especially clock signals. Avoid
routing digital lines underneath the MAX5703/MAX5704/
MAX5705 package.
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
Maxim Integrated
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
DD
with high-quality ceramic capacitors to
Applications Information
Power Supplies and Bypassing
Integral Nonlinearity (INL)
Table 1
Layout Considerations
Power-On Reset (POR)
DD
and
RETURN Command
, the DAC output is
Table
Considerations
Definitions
2.
MAX5703/MAX5704/MAX5705
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL P
1 LSB, the DAC guarantees no missing codes and is
monotonic. If the magnitude of the DNL R 1 LSB, the DAC
output may still be monotonic.
Offset error indicates how well the actual transfer function
matches the ideal transfer function. The offset error is
calculated from two measurements near zero code and
near maximum code.
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Zero-scale error is the difference between the DAC
output voltage when set to code zero and ground. This
includes offset and other die level nonidealities.
Full-scale error is the difference between the DAC output
voltage when set to full scale and the reference voltage.
This includes offset, gain error, and other die level
nonidealities.
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse.
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
Digital-to-Analog Glitch Impulse
Differential Nonlinearity (DNL)
Digital Feedthrough
Zero-Scale Error
Full-Scale Error
Settling Time
Offset Error
Gain Error
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