MAX5802AAUB+T Maxim Integrated, MAX5802AAUB+T Datasheet - Page 17

• Manufacturer Part Number: MAX5802AAUB+T
• Description: Digital to Analog Converters - DAC 12-Bit 2Ch DAC w/I2C
• Manufacturer: Maxim Integrated

Specifications of MAX5802AAUB+T

• Rohs: yes

The slave address is defined as the seven most sig-
nificant bits (MSBs) followed by the R/W bit. See
4. The five most significant bits are 00011 with the 2
LSBs determined by ADDR as shown in
the R/W bit to 1 configures the MAX5800/MAX5801/
MAX5802 for read mode. Setting the R/W bit to 0 config-
ures the MAX5800/MAX5801/MAX5802 for write mode.
The slave address is the first byte of information sent
to the MAX5800/MAX5801/MAX5802 after the START
condition.
The MAX5800/MAX5801/MAX5802 have the ability to
detect an unconnected state on the ADDR input for
additional address flexibility; if leaving the ADDR input
unconnected, be certain to minimize all loading on the
pin (i.e. provide a landing for the pin, but do not allow
any board traces).
A broadcast address is provided for the purpose of
updating or configuring all MAX5800/MAX5801/MAX5802
devices on a given I
MAX5802 devices acknowledge and respond to the
broadcast device address 00010000. The devices will
respond to the broadcast address, regardless of the
state of the address pins. The broadcast mode is intend-
ed for use in write mode only (as indicated by R/W = 0 in
the address given).
In write mode, the acknowledge bit (ACK) is a clocked 9th
bit that the MAX5800/MAX5801/MAX5802 use to hand-
Figure 4. I
Maxim Integrated
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
SDA
SCL
2
C Single Register Write Sequence
START
DACs with Internal Reference and I
BYTE #1: I
0
WRITE ADDRESS
0
2
2
C SLAVE ADDRESS
0
C bus. All MAX5800/MAX5801/
1 1 A1 A0
I
A
2
C Broadcast Address
ACK. GENERATED BY MAX5800/MAX5801/MAX5802
I
I
2
W
2
C Slave Address
C Acknowledge
A
23
BYTE #2: COMMAND BYTE
Table
22
WRITE COMMAND
21
(B[23:16])
20 19 18 17
1. Setting
Figure
MAX5800/MAX5801/MAX5802
16
A
15 14 13 12 11 10 9
BYTE #3: DATA HIGH BYTE
Table 1. I
shake receipt of each byte of data as shown in
The MAX5800/MAX5801/MAX5802 pull down SDA during
the entire master-generated 9th clock pulse if the previous
byte is successfully received. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuccessful
data transfer occurs if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccess-
ful data transfer, the bus master will retry communication.
Figure 3. I
SDA
SCL
CONDITION
WRITE DATA
START
(B[15:8])
ADDR
V
GND
N.C.
DDIO
2
C Acknowledge
2
C Slave Address LSBs
8
1
A
7 6 5 4 3 2 1
BYTE #4: DATA LOW BYTE
A[6:2] = 00011
2
WRITE DATA
(B[7:0])
A1
0
1
1
2
NOT ACKNOWLEDGE
C Interface
ACKNOWLEDGE
0
A
ACKNOWLEDGMENT
COMMAND EXECUTED
CLOCK PULSE
STOP
FOR
9
A0
0
0
1
Figure
17
3.