MAX5802AAUB+T Maxim Integrated, MAX5802AAUB+T Datasheet - Page 21

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MAX5802AAUB+T

Manufacturer Part Number
MAX5802AAUB+T
Description
Digital to Analog Converters - DAC 12-Bit 2Ch DAC w/I2C
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX5802AAUB+T

Rohs
yes
Table 3. Format DAC Data Bit Positions
SCL line but the MAX5800/MAX5801/MAX5802 take over
the SDA line. The final three bytes in the frame contain
the command and register data written in the first transfer
presented for readback, followed by a STOP condition. If
additional bytes beyond those required to read back the
requested data are provided, the MAX5800/MAX5801/
MAX5802 will continue to read back ones.
It is not necessary for the write and read mode transfers
to occur immediately in sequence. I
ing other devices do not impact the MAX5800/MAX5801/
MAX5802 readback mode. Toggling between readback
modes is based on the length of the preceding write
mode transfer. Combined format I
is resumed if a write command greater than two bytes
but less than four bytes is supplied. For commands writ-
ten using multiple register write sequences, only the last
command executed is read back. For each command
written, the readback sequence can only be completed
one time; partial and/or multiple attempts to readback
executed in succession will not yield usable data.
The MAX5800/MAX5801/MAX5802 are fully compatible
with existing I
ance inputs; SDA has an open drain which pulls the data
line low to transmit data or ACK pulses.
typical I
This section lists the user accessible commands and
registers for the MAX5800/MAX5801/MAX5802. Each
serial operation word is 24-bits long. The DAC data is left
justified as shown in Table 3.
Table 4
Registers.
Maxim Integrated
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
MAX5800
MAX5801
MAX5802
PART
provides detailed information about the Command
2
C application.
2
C systems. SCL and SDA are high-imped-
I
B15
D11
D7
D9
2
DACs with Internal Reference and I
C User-Command Register Map
B14
D10
D6
D8
B13
D5
D7
D9
2
B12
C readback operation
I
D4
D6
D8
2
C Compatibility
2
C transfers involv-
Figure 8
B11
D3
D5
D7
B10
D2
D4
D6
shows a
MAX5800/MAX5801/MAX5802
B9
D1
D3
D5
B8
D0
D2
D4
Figure 8. Typical I
B7
D1
D3
X
+5V
B6
D0
D2
X
2
C Application Circuit
SDA
D1
B5
X
X
µC
SCL
B4
D0
X
X
2
B3
C Interface
X
X
X
SCL
SDA
ADDR
SCL
SDA
ADDR
B2
X
X
X
B1
X
X
X
B0
X
X
X
21

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