DAC1008D750HN/C1 NXP Semiconductors, DAC1008D750HN/C1 Datasheet - Page 73

• Manufacturer Part Number: DAC1008D750HN/C1
• Description: Digital to Analog Converters - DAC DL 10BIT DAC 750MSPS 2X 4X OR 8X INT
• Manufacturer: NXP Semiconductors

Specifications of DAC1008D750HN/C1

• Rohs: yes
• Factory Pack Quantity: 260

NXP Semiconductors
Table 118. K28_LN3_FLAG register (address 09h) bit description
Table 119. KOUT_UNEXPECTED_FLAG register (address 0Ah) bit description
Table 120. LOCK_CNT_MON_LN01 register (address 0Bh) bit description
Default settings are shown highlighted.
Table 121. LOCK_CNT_MON_LN23 register (address 0Ch) bit description
Default settings are shown highlighted.
Table 122. CS_STATE_LNX register (address 0Dh) bit description
Default settings are shown highlighted.
Table 123. RST_BUF_ERR_FLAGS register (address 0Eh) bit description
Default settings are shown highlighted.
DAC1008D750
Product data sheet
Bit
4
3
2
1
0
Bit
3
2
1
0
Bit
7 to 4
3 to 0
Bit
7 to 4
3 to 0
Bit
7 to 6
5 to 4
3 to 2
1 to 0
Bit
7
Symbol
K28_7_LN3
K28_5_LN3
K28_4_LN3
K28_3_LN3
K28_0_LN3
Symbol
DEC_KOUT_UNEXP_LN3
DEC_KOUT_UNEXP_LN2
DEC_KOUT_UNEXP_LN1
DEC_KOUT_UNEXP_LN0
Symbol
LOCK_CNT_MON_LN1[3:0]
LOCK_CNT_MON_LN0[3:0]
Symbol
LOCK_CNT_MON_LN3[3:0]
LOCK_CNT_MON_LN2[3:0]
Symbol
CS_STATE_LN3[1:0]
CS_STATE_LN2[1:0]
CS_STATE_LN1[1:0]
CS_STATE_LN0[1:0]
Symbol
RST_BUF_ERR_FLAGS
All information provided in this document is subject to legal disclaimers.
Access
R
R
R
R
R
Access
R
R
R
R
Access
R
R
Access
R
R
Access
R
R
R
R
Access
R/W
Rev. 3 — 31 January 2012
Value
-
-
-
-
-
Value
-
-
-
-
Value
-
-
Value
-
-
Value
-
-
-
-
Value
0
2, 4 or 8 interpolating DAC with JESD204A
Description
K28_7 /F/ symbols found in lane 3
K28_5 /K/ symbols found in lane 3
K28_4 /Q/ symbols found in lane 3
K28_3 /A/ symbols found in lane 3
K28_0 /R/ symbols found in lane 3
Description
unexpected /K/ symbols found in lane 3
unexpected /K/ symbols found in lane 2
unexpected /K/ symbols found in lane 1
unexpected /K/ symbols found in lane 0
Description
lock_state monitor synchronization word alignment
lane 1
lock_state monitor synchronization word alignment
lane 0
Description
lock_state monitor synchronization word alignment
lane 3
lock_state monitor synchronization word alignment
lane 2
Description
monitor cs_state fsm lane 3 (see
monitor cs_state fsm lane 2 (see
monitor cs_state fsm lane 1 (see
monitor cs_state fsm lane 0 (see
Description
reset ILA_BUF_ERR_LNn flags
DAC1008D750
© NXP B.V. 2012. All rights reserved.
Table
Table
Table
Table
142)
142)
142)
142)
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