MAX5580AEUP-T Maxim Integrated, MAX5580AEUP-T Datasheet - Page 27

• Manufacturer Part Number: MAX5580AEUP-T
• Description: Digital to Analog Converters - DAC
• Manufacturer: Maxim Integrated

Specifications of MAX5580AEUP-T

• Number Of Converters: 4
• Number Of Dac Outputs: 4
• Resolution: 12 bit
• Interface Type: QSPI, SPI, Serial (3-Wire, Microwire)
• Settling Time: 6 us
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP EP
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 2.7 V
• Voltage Reference: External

The MAX5580–MAX5585 provide two user-programma-
ble input/output (UPIO) ports: UPIO1 and UPIO2. These
ports have 15 possible configurations, as shown in
Table 21. UPIO1 and UPIO2 can be programmed inde-
pendently or simultaneously by writing to the UPSL1,
UPSL2, and UP0–UP3 bits (Table 17).
Table 18 shows how UPIO1 and UPIO2 are selected for
configuration. The UP0–UP3 bits select the desired
functions for UPIO1 and/or UPIO2 (Table 21).
Table 17. UPIO Write Command
X = Don’t care.
Table 18. UPIO Selection Bits (UPSL1 and UPSL2)
Table 19. UPIO Programming Example
X = Don’t care.
Table 20. UPIO Read Command
X = Don’t care.
DOUTRB
DATA
DATA
DATA
DIN
DIN
DIN
1
1
UPSL2
1
X
0
0
1
1
UPIO Bits (UPSL1, UPSL2, UP0–UP3)
1
1
1
X
______________________________________________________________________________________
1
1
X
1
CONTROL BITS
CONTROL BITS
CONTROL BITS
0
0
X
0
12-/10-/8-Bit, Voltage-Output DACs
1
1
X
1
UPSL1
0
1
0
1
0
0
Buffered, Fast-Settling, Quad,
0
X
0
0
1
X
X
X
X
X
UPIO Programming Example:
To set only UPIO1 as LDAC and leave UPIO2
unchanged, use the command in Table 19.
The UPIO selection and configuration bits can be read
back from the MAX5580–MAX5585 when UPIO1 or
UPIO2 is configured as a DOUTRB output. Table 20
shows the read-back data format for the UPIO bits.
Writing the command in Table 20 initiates a read opera-
tion of the UPIO bits. The data is clocked out starting on
the 9th clock cycle of the sequence. Bits UP3-2 through
UP0-2 provide the UP3–UP0 configuration bits for
UPIO2 (Table 21), and bits UP3-1 through UP0-1 pro-
vide the UP3–UP0 configuration bits for UPIO1.
U P S L2 U P S L1
U P 3- 2 U P 2- 2 U P 1- 2 U P 0- 2 U P 3- 1 U P 2- 1 U P 1- 1 U P 0- 1
0
X
1
X
Both UPIO1 and UPIO2 selected
UPIO PORT SELECTED
UP3
0
X
UPIO1 selected
UPIO2 selected
None selected
DATA BITS
UP2
DATA BITS
DATA BITS
0
X
UP1
0
X
UP0
0
X
X
X
X
X
X
X
27