MAX5580AEUP-T Maxim Integrated, MAX5580AEUP-T Datasheet - Page 7

• Manufacturer Part Number: MAX5580AEUP-T
• Description: Digital to Analog Converters - DAC
• Manufacturer: Maxim Integrated

Specifications of MAX5580AEUP-T

• Number Of Converters: 4
• Number Of Dac Outputs: 4
• Resolution: 12 bit
• Interface Type: QSPI, SPI, Serial (3-Wire, Microwire)
• Settling Time: 6 us
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP EP
• Minimum Operating Temperature: - 40 C
• Output Type: Voltage
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 2.7 V
• Voltage Reference: External

TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)
(DV DD = 1.8V to 2.7V, AGND = DGND = 0, T A = T MIN to T MAX , unless otherwise noted.)
SCLK Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SCLK Rise to CS Fall Setup TIme
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Rise to DOUTDC1 Valid
Propagation Delay
SCLK Fall to DOUT_ Valid
Propagation Delay
CS Rise to SCLK Rise Hold Time
CS Pulse-Width High
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
DOUTRB Tri-State Time from CS
Rise
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
LDAC Pulse-Width Low
LDAC Effective Delay
CLR, MID, SET Pulse-Width Low
GPO Output Settling Time
GPO Output High-Impedance
Time
PARAMETER
_______________________________________________________________________________________
SYMBOL
12-/10-/8-Bit, Voltage-Output DACs
t
f
t
t
t
t
t
t
DRBZ
t
SCLK
t
t
t
t
t
t
CSW
CMS
t
CSH
t
DO1
DO2
DOZ
t
GPZ
t
CSS
CS0
t
CS1
ZEN
LDL
LDS
CH
DH
CL
DS
GP
1.8V < DV
(Note 7)
(Note 7)
C
C
mode
MICROWIRE and SPI modes 0 and 3
C
in high impedance
C
in high impedance
C
UPIO_ driven out of tri-state
Figure 5
Figure 6
Figure 5
Figure 6
Buffered, Fast-Settling, Quad,
L
L
L
L
L
= 20pF, UPIO_ = DOUTDC1 mode
= 20pF, UPIO_ = DOUTDC0 or DOUTRB
= 20pF, from end of write cycle to UPIO_
= 20pF, from rising edge of CS to UPIO_
= 20pF, from 8th rising edge of SCLK to
DD
< 2.7V
CONDITIONS
MIN
200
40
40
20
10
20
20
90
40
40
5
5
0
TYP
MAX
200
200
200
10
60
40
60
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7