CAV25160VE-GT3 ON Semiconductor, CAV25160VE-GT3 Datasheet
CAV25160VE-GT3
Specifications of CAV25160VE-GT3
Related parts for CAV25160VE-GT3
CAV25160VE-GT3 Summary of contents
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... Page Write Buffer • Self−timed Write Cycle • Hardware and Software Protection • Block Write Protection − Protect 1/4, 1/2 or Entire EEPROM Array • Low Power CMOS Technology • 1,000,000 Program/Erase Cycles • 100 Year Data Retention • Industrial and Extended Temperature Range • ...
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AYMXXX G (SOIC−8) 25080D = CAV25080 25160D = CAV25160 A = Assembly Location Y = Production Year (Last Digit Production Month (1− XXX = Last Three Digits of XXX = Assembly Lot Number = ...
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Table 4. PIN CAPACITANCE (T = 25° 1.0 MHz Symbol Test C Output Capacitance (SO) OUT C Input Capacitance (CS, SCK, SI, WP, HOLD) IN Table 5. A.C. CHARACTERISTICS Symbol f Clock Frequency SCK t Data ...
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Pin Description SI: The serial data input pin accepts op−codes, addresses and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of the SCK clock input. SO: The serial data output pin is used ...
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Table 8. STATUS REGISTER WPEN 0 0 Table 9. BLOCK PROTECTION BITS Status Register Bits BP1 BP0 Table 10. WRITE PROTECT CONDITIONS WPEN ...
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The CAV25080/160 device powers up into a write disable state. The device contains a Write Enable Latch (WEL) which must be set before attempting to write to the memory array or to the status register. In addition, the address of ...
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Byte Write Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 16−bit address and data as shown in Figure 5. Only 10 significant address bits are used by the CAV25080 ...
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Write Status Register The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits 2, 3 and 7 can be written using the WRSR command SCK OPCODE ...
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Read from Memory Array To read from memory, the host sends a READ instruction followed by a 16−bit address (see Table 11 for the number of significant address bits). After receiving the last address bit, the CAV25080/160 will respond by ...
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Hold Operation The HOLD input can be used to pause communication between host and CAV25080/160. To pause, HOLD must be taken low while SCK is low (Figure 11). During the hold condition the device must remain selected (CS low). During ...
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PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...
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E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...
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... Number Marking CAV25080VE−GT3 25080D CAV25080YE−GT3 S08D CAV25160VE−GT3 25160D CAV25160YE−GT3 S16D 8. All packages are RoHS−compliant (Lead−free, Halogen−free). 9. The standard lead finish is NiPdAu. 10. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. ...