CAV25160VE-GT3 ON Semiconductor, CAV25160VE-GT3 Datasheet - Page 6

• Manufacturer Part Number: CAV25160VE-GT3
• Description: EEPROM 16KB SPI SER CMOS EEPROM
• Manufacturer: ON Semiconductor

Specifications of CAV25160VE-GT3

• Product Category: EEPROM

state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
Write Enable and Write Disable
Status Register WEL bit are set by sending the WREN
The CAV25080/160 device powers up into a write disable
The internal Write Enable Latch and the corresponding
SCK
SO
CS
SI
SCK
SO
CS
SI
Dashed Line = mode (1, 1)
Dashed Line = mode (1, 1)
0
0
Figure 3. WREN Timing
WRITE OPERATIONS
0
0
Figure 4. WRDI Timing
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0
0
HIGH IMPEDANCE
0
0
HIGH IMPEDANCE
6
0
0
instruction to the CAV25080/160. Care must be taken to take
the CS input high after the WREN instruction, as otherwise
the Write Enable Latch will not be properly set. WREN
timing is illustrated in Figure 3. The WREN instruction must
be sent prior to any WRITE or WRSR instruction.
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
1
The internal write enable latch is reset by sending the
1
1
0
0
0