CAT25512HU5I-GT3 ON Semiconductor, CAT25512HU5I-GT3 Datasheet
CAT25512HU5I-GT3
Specifications of CAT25512HU5I-GT3
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CAT25512HU5I-GT3 Summary of contents
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... SPI Serial CMOS EEPROM Description The CAT25512 is a 512−Kb Serial CMOS EEPROM device internally organized as 64Kx8 bits. This features a 128−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines ...
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Table 1. ABSOLUTE MAXIMUM RATINGS Operating Temperature Storage Temperature Voltage on any Pin with Respect to Ground (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions ...
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Table 4. PIN CAPACITANCE (T = 25° 1.0 MHz Symbol Test C Output Capacitance (SO) OUT C Input Capacitance (CS, SCK, SI, WP, HOLD) IN Table 5. A.C. CHARACTERISTICS Symbol Parameter f Clock Frequency SCK t ...
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Pin Description SI: The serial data input pin accepts op−codes, addresses and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of the SCK clock input. SO: The serial data output pin is used ...
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Status Register The Status Register, as shown in Table 8, contains a number of status and control bits. The RDY (Ready) bit indicates whether the device is busy with a write operation. This bit is automatically set to 1 during ...
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The CAT25512 device powers up into a write disable state. The device contains a Write Enable Latch (WEL) which must be set before attempting to write to the memory array or to the status register. In addition, the address of ...
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Byte Write Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 16−bit address and a data byte as shown in Figure 5. Internal programming will start after the low to ...
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Write Status Register The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits and 7 can be written using the WRSR command. The internal programming for the ...
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Read from Memory Array To read from memory, the host sends a READ instruction followed by a 16−bit address. After receiving the last address bit, the CAT25512 will respond by shifting out data on the SO pin (as shown in ...
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Hold Operation The HOLD input can be used to pause communication between host and CAT25512. To pause, HOLD must be taken low while SCK is low (Figure 11). During the hold condition the device must remain selected (CS low). During ...
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PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...
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PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...
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E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...
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PIN#1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL ...
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Í Í Í E PIN 1 Í Í Í REFERENCE Í Í Í 0.15 C Í Í Í 0.15 C TOP VIEW DETAIL NOTE 4 C SIDE VIEW 0.10 M ...
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... Device Order Device Number Marking CAT25512LE−G 25512A CAT25512LI−G 25512A CAT25512LI−GL 25512A CAT25512HU5E−GT3 S9L CAT25512HU5I−GT3 S9L CAT25512HU5I−GT3L S9L CAT25512VE−GT3 25512A CAT25512VI−GT3 25512A CAT25512VI−GT3L 25512A CAT25512XE−T2 25512A CAT25512XI−T2 25512A CAT25512XI−T2L 25512A CAT25512YE− ...