CAT25256ZD2I-GT2 ON Semiconductor, CAT25256ZD2I-GT2 Datasheet - Page 8
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CAT25256ZD2I-GT2
Manufacturer Part Number
CAT25256ZD2I-GT2
Description
EEPROM 256KB SPI SER CMOS EEPROM
Manufacturer
ON Semiconductor
Datasheet
1.CAT25256ZD2I-GT2.pdf
(20 pages)
Specifications of CAT25256ZD2I-GT2
Rohs
yes
Memory Size
256 Kbit
Organization
32 x 8
Data Retention
100 yr
Maximum Clock Frequency
1000 KHz
Maximum Operating Current
2 mA
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TDFN-8
Interface Type
SPI
Minimum Operating Temperature
- 40 C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CAT25256ZD2I-GT2
Manufacturer:
ON/安森美
Quantity:
20 000
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
Write Enable and Write Disable
Status Register WEL bit are set by sending the WREN
The CAT25256 device powers up into a write disable
The internal Write Enable Latch and the corresponding
SCK
SO
CS
SI
SCK
SO
CS
SI
Dashed Line = mode (1, 1)
Dashed Line = mode (1, 1)
0
0
Figure 3. WREN Timing
WRITE OPERATIONS
0
0
Figure 4. WRDI Timing
http://onsemi.com
0
0
HIGH IMPEDANCE
0
0
HIGH IMPEDANCE
8
0
0
instruction to the CAT25256. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
1
The internal write enable latch is reset by sending the
1
1
0
0
0