M95040-RMC6TG STMicroelectronics, M95040-RMC6TG Datasheet - Page 18

• Manufacturer Part Number: M95040-RMC6TG
• Description: EEPROM 4 Kbit SPI BUS EE 10MHz CR 5ms
• Manufacturer: STMicroelectronics

Specifications of M95040-RMC6TG

• Product Category: EEPROM
• Rohs: yes

Instructions
6.3
6.3.1
6.3.2
6.3.3
18/44
Read Status Register (RDSR)
The Read Status Register instruction is used to read the Status Register.
As shown in
The bits of the instruction byte are then shifted in, on Serial Data Input (D). The current state
of the bits in the Status register is shifted out, on Serial Data Out (Q). The Read Cycle is
terminated by driving Chip Select (S) high.
The Status Register is always readable, even if a Write or Write Status Register cycle is in
progress. During a Write Status Register cycle, the values of the non-volatile bits (BP0,
BP1) become available when a new RDSR instruction is executed, after completion of the
Write cycle. On the other hand, the two read-only bits (Write Enable Latch (WEL), Write In
Progress (WIP)) are dynamically updated during the ongoing Write cycle.
It is also possible to read the Status Register contents continuously, as described in
Figure
Bits b7, b6, b5 and b4 are always read as 1. The status and control bits of the Status
register are as follows:
Table 5.
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in
protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set.
b7
1
9.
Figure
Status register format
1
9, to send this instruction to the device, Chip Select (S) is first driven low.
1
Doc ID 6512 Rev 10
1
Table 3: Write-protected block
BP1
Block Protect bits
Write Enable Latch bit
M950x0 M950x0-W M950x0-R
BP0
WEL
Write In Progress bit
size) becomes
WIP
b0