LCMXO2-1200HC-4TG100I Lattice, LCMXO2-1200HC-4TG100I Datasheet - Page 33
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LCMXO2-1200HC-4TG100I
Manufacturer Part Number
LCMXO2-1200HC-4TG100I
Description
FPGA - Field Programmable Gate Array 1280 LUTs 80 I/O 3.3V -4 SPD
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-1200HC-4TG100I
Rohs
yes
Number Of Gates
1.2 K
Embedded Block Ram - Ebr
64 Kbit
Number Of I/os
80
Maximum Operating Frequency
269 MHz
Operating Supply Voltage
1.14 V to 3.465 V, 2.375 V to 3.465 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
TQFP-100
Distributed Ram
10 Kbit
Minimum Operating Temperature
- 40 C
Operating Supply Current
3.49 mA
Factory Pack Quantity
90
User Flash Memory - Ufm
64 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-1200HC-4TG100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO2-1200HC-4TG100I
Manufacturer:
LATTICE/莱迪斯
Quantity:
20 000
Company:
Part Number:
LCMXO2-1200HC-4TG100IR1
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Figure 2-21. I
Table 2-15 describes the signals interfacing with the I
Table 2-15. I
Hardened SPI IP Core
Every MachXO2 device has a hard SPI IP core that can be configured as a SPI master or slave. When the IP core
is configured as a master it will be able to control other SPI enabled chips connected to the SPI bus. When the core
is configured as the slave, the device will be able to interface to an external SPI master. The SPI IP core on
MachXO2 devices supports the following functions:
i2c_scl
i2c_sda
i2c_irqo
cfg_wake
cfg_stdby
Signal Name
• Configurable Master and Slave modes
• Full-Duplex data transfer
• Mode fault error flag with CPU interrupt capability
• Double-buffered data register
• Serial clock with programmable polarity and phase
• LSB First or MSB First Data Transfer
• Interface to custom logic through 8-bit WISHBONE interface
2
C Core Signal Description
2
C Core Block Diagram
Bi-directional
Bi-directional
Output
Output
Output
I/O
Routing
Logic/
Core
Bi-directional clock line of the I
mode. The signal is an input if the I
pre-assigned I/O of the chip. Refer to the Pinout Information section of this document for
detailed pad and pin locations of I
Bi-directional data line of the I
the I
directly to the pre-assigned I/O of the chip. Refer to the Pinout Information section of this
document for detailed pad and pin locations of I
Interrupt request output signal of the I
connected to the WISHBONE master controller (i.e. a microcontroller or state machine) and
request an interrupt when a specific condition is met. These conditions are described with
the I
Wake-up signal – To be connected only to the power module of the MachXO2 device. The
signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I
Tab.
Stand-by signal – To be connected only to the power module of the MachXO2 device. The
signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I
Tab.
2
2
C core. The signal is an input when data is received into the I
C register definitions.
EFB
WISHBONE
Interface
EFB
2
Configuration
C cores.
2-29
Registers
Logic
2
I
2
C core. The signal is an output when data is transmitted from
2
C core. The signal is an output if the I
C
2
I
C ports in each MachXO2 device.
2
2
C Function
C core is in slave mode. MUST be routed directly to the
2
C core. The intended usage of this signal is for it to be
Description
Control
Control
Power
Logic
2
C ports in each MachXO2 device.
MachXO2 Family Data Sheet
SDA
SCL
2
C core. MUST be routed
2
C core is in master
Architecture
2
2
C
C