LCMXO2-2000ZE-1MG132C Lattice, LCMXO2-2000ZE-1MG132C Datasheet - Page 11
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LCMXO2-2000ZE-1MG132C
Manufacturer Part Number
LCMXO2-2000ZE-1MG132C
Description
FPGA - Field Programmable Gate Array 2112 LUTs 105 IO 1.2V 1 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-2000ZE-1MG132C
Rohs
yes
Number Of Gates
2 K
Embedded Block Ram - Ebr
74 Kbit
Number Of I/os
105
Maximum Operating Frequency
104 MHz
Operating Supply Voltage
1.14 V to 1.26 V, 1.14 V to 3.465 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
csBGA-132
Distributed Ram
16 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
80 uA
Factory Pack Quantity
360
User Flash Memory - Ufm
80 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-2000ZE-1MG132C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Eight secondary high fanout nets are generated from eight 8:1 muxes as shown in Figure 2-6. One of the eight
inputs to the secondary high fanout net input mux comes from dual function clock pins and the remaining seven
come from internal routing. The maximum frequency for the secondary clock network is shown in MachXO2 Exter-
nal Switching Characteristics table.
Figure 2-6. Secondary High Fanout Nets for MachXO2 Devices
sysCLOCK Phase Locked Loops (PLLs)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The MachXO2-640U, MachXO2-1200/U
and larger devices have one or more sysCLOCK PLL. CLKI is the reference frequency input to the PLL and its
source can come from an external I/O pin or from internal routing. CLKFB is the feedback signal to the PLL which
can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference fre-
quency and thus synthesize a higher frequency clock output.
The MachXO2 sysCLOCK PLLs support high resolution (16-bit) fractional-N synthesis. Fractional-N frequency syn-
thesis allows the user to generate an output clock which is a non-integer multiple of the input frequency. For more
information about using the PLL with Fractional-N synthesis, please see TN1199,
Design and Usage
Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The
output dividers can have a value from 1 to 128. The CLKOS2 and CLKOS3 dividers may also be cascaded together
to generate low frequency clocks. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the
MachXO2 clock distribution network directly or general purpose routing resources can be used.
Guide.
Clock Pads
1
Routing
7
2-7
8:1
8:1
8:1
8:1
8:1
8:1
8:1
8:1
Secondary High
Secondary High
Secondary High
Secondary High
Secondary High
Secondary High
Secondary High
Secondary High
Fanout Net 0
Fanout Net 1
Fanout Net 2
Fanout Net 3
Fanout Net 4
Fanout Net 5
Fanout Net 6
Fanout Net 7
MachXO2 Family Data Sheet
MachXO2 sysCLOCK PLL
Architecture