LCMXO2-2000ZE-1MG132C Lattice, LCMXO2-2000ZE-1MG132C Datasheet - Page 66
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LCMXO2-2000ZE-1MG132C
Manufacturer Part Number
LCMXO2-2000ZE-1MG132C
Description
FPGA - Field Programmable Gate Array 2112 LUTs 105 IO 1.2V 1 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-2000ZE-1MG132C
Rohs
yes
Number Of Gates
2 K
Embedded Block Ram - Ebr
74 Kbit
Number Of I/os
105
Maximum Operating Frequency
104 MHz
Operating Supply Voltage
1.14 V to 1.26 V, 1.14 V to 3.465 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
csBGA-132
Distributed Ram
16 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
80 uA
Factory Pack Quantity
360
User Flash Memory - Ufm
80 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-2000ZE-1MG132C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered
t
t
f
f
f
Generic DDRX4 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Aligned
t
t
f
f
f
Generic DDRX4 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Centered
t
t
f
f
f
7:1 LVDS Outputs – GDDR71_TX.ECLK.7:1
t
t
f
f
f
DVB
DVA
DATA
DDRX2
SCLK
DIA
DIB
DATA
DDRX4
SCLK
DVB
DVA
DATA
DDRX4
SCLK
DVB
DVA
DATA
DDR71
CLKOUT
Parameter
Output Data Valid Before CLK
Output
Output Data Valid After CLK
Output
DDRX2 Serial Output Data
Speed
DDRX2 ECLK Frequency
(minimum limited by PLL)
SCLK Frequency
Output Data Invalid After CLK
Output
Output Data Invalid Before
CLK Output
DDRX4 Serial Output Data
Speed
DDRX4 ECLK Frequency
SCLK Frequency
Output Data Valid Before CLK
Output
Output Data Valid After CLK
Output
DDRX4 Serial Output Data
Speed
DDRX4 ECLK Frequency
(minimum limited by PLL)
SCLK Frequency
Output Data Valid Before CLK
Output
Output Data Valid After CLK
Output
DDR71 Serial Output Data
Speed
DDR71 ECLK Frequency
7:1 Output Clock Frequency
(SCLK) (minimum limited by
PLL)
Description
9
MachXO2-640U,
MachXO2-1200/U
and larger devices,
top side only
MachXO2-640U,
MachXO2-1200/U
and larger devices,
top side only
MachXO2-640U,
MachXO2-1200/U
and larger devices,
top side only
MachXO2-640U,
MachXO2-1200/U
and larger devices,
top side only.
Device
3-27
1.445
1.445
0.873
0.873
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-3
DC and Switching Characteristics
0.270
0.270
0.240
0.240
Max.
280
140
420
210
420
210
420
210
—
—
70
53
—
—
53
60
MachXO2 Family Data Sheet
1.760
1.760
1.067
1.067
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-2
0.300
0.300
0.270
0.270
Max.
234
117
352
176
352
176
352
176
59
44
44
50
—
—
—
—
2.140
2.140
1.319
1.319
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-1
0.330
0.330
0.300
0.300
Max.
194
292
146
292
146
292
146
97
49
37
37
42
—
—
—
—
Units
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
9
9
9