LFE3-35EA-7LFN672C Lattice, LFE3-35EA-7LFN672C Datasheet - Page 106
LFE3-35EA-7LFN672C
Manufacturer Part Number
LFE3-35EA-7LFN672C
Description
FPGA - Field Programmable Gate Array 33.3K LUTs 310 I/O 1.2V -7 SPEED
Manufacturer
Lattice
Datasheet
1.LFE3-95EA-7LFN672I.pdf
(141 pages)
Specifications of LFE3-35EA-7LFN672C
Rohs
yes
Number Of Gates
33 K
Number Of Logic Blocks
72
Embedded Block Ram - Ebr
1327 Kbit
Number Of I/os
310
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
FPBGA-672
Distributed Ram
68 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
53.7 mA
Factory Pack Quantity
40
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-35EA-7LFN672C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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LatticeECP3 sysCONFIG Port Timing Specifications (Continued)
Figure 3-20. sysCONFIG Parallel Port Read Cycle
t
Master and Slave SPI (Continued)
t
t
t
t
1. Re-toggling the PROGRAMN pin is not permitted until the INITN pin is high. Avoid consecutive toggling of the PROGRAMN.
Master Clock Frequency
Duty Cycle
Parameter
CHHH
CHHL
HHCH
HLQZ
HHQX
Parameter
HOLDN Low Hold Time (Relative to CCLK)
HOLDN High Hold Time (Relative to CCLK)
HOLDN High Setup Time (Relative to CCLK)
HOLDN to Output High-Z
HOLDN to Output Low-Z
WRITEN
CCLK
CS1N
BUSY
D[0:7]
*n = last byte of read cycle.
CSN
Selected value - 15%
Over Recommended Operating Conditions
Min.
40
t
t
SUCS
SUWD
Description
Byte 0
t
BSCL
3-53
Byte 1
t
CORD
Selected value + 15%
Max.
t
60
DCB
DC and Switching Characteristics
t
Byte 2
BSCYC
t
BSCH
LatticeECP3 Family Data Sheet
Byte n*
t
t
HCS
HWD
Min.
—
—
5
5
5
Units
MHz
%
Max.
—
—
—
9
9
Units
ns
ns
ns
ns
ns
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