LCMXO2-1200ZE-1TG100I Lattice, LCMXO2-1200ZE-1TG100I Datasheet - Page 58
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LCMXO2-1200ZE-1TG100I
Manufacturer Part Number
LCMXO2-1200ZE-1TG100I
Description
FPGA - Field Programmable Gate Array 1280 LUTs 80 I/O 1.2V -1 SPD
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-1200ZE-1TG100I
Rohs
yes
Number Of Gates
1.2 K
Embedded Block Ram - Ebr
64 Kbit
Number Of I/os
80
Maximum Operating Frequency
104 MHz
Operating Supply Voltage
1.14 V to 3.465 V, 2.375 V to 3.465 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
TQFP-100
Distributed Ram
10 Kbit
Minimum Operating Temperature
- 40 C
Operating Supply Current
56 uA
Factory Pack Quantity
90
User Flash Memory - Ufm
64 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-1200ZE-1TG100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LCMXO2-1200ZE-1TG100IR1
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
t
t
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Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Aligned
t
t
f
f
Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Centered
t
t
f
f
Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Aligned
t
t
f
f
f
Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Centered
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t
f
f
f
HPLL
SU_DELPLL
H_DELPLL
DVA
DVE
DATA
DDRX1
SU
HO
DATA
DDRX1
DVA
DVE
DATA
DDRX2
SCLK
SU
HO
DATA
DDRX2
SCLK
Parameter
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO
Input Register with Data Input
Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Input Data Valid After CLK
Input Data Hold After CLK
DDRX1 Input Data Speed
DDRX1 SCLK Frequency
Input Data Setup Before CLK
Input Data Hold After CLK
DDRX1 Input Data Speed
DDRX1 SCLK Frequency
Input Data Valid After CLK
Input Data Hold After CLK
DDRX2 Serial Input Data
Speed
DDRX2 ECLK Frequency
SCLK Frequency
Input Data Setup Before CLK
Input Data Hold After CLK
DDRX2 Serial Input Data
Speed
DDRX2 ECLK Frequency
SCLK Frequency
Description
MachXO2-1200HC-HE
MachXO2-2000HC-HE
MachXO2-4000HC-HE
MachXO2-7000HC-HE
MachXO2-1200HC-HE
MachXO2-2000HC-HE
MachXO2-4000HC-HE
MachXO2-7000HC-HE
MachXO2-1200HC-HE -0.83
MachXO2-2000HC-HE -0.83
MachXO2-4000HC-HE -0.87
MachXO2-7000HC-HE -0.91
All MachXO2 devices,
all sides
All MachXO2 devices,
all sides
MachXO2-640U,
MachXO2-1200/U and
larger devices,
bottom side only
MachXO2-640U,
MachXO2-1200/U and
larger devices,
bottom side only
Device
3-19
0.742
0.778
0.710
0.287
0.566
0.233
Min.
0.41
0.42
0.43
0.46
2.88
2.87
2.96
3.05
—
—
—
—
—
—
—
—
—
—
—
—
-6
DC and Switching Characteristics
0.317
0.316
Max.
300
150
300
150
664
332
166
664
332
166
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MachXO2 Family Data Sheet
0.702
0.560
0.879
0.675
0.219
0.287
-0.83
-0.83
-0.87
-0.91
Min.
0.48
0.49
0.50
0.54
3.19
3.18
3.28
3.35
—
—
—
—
—
—
—
—
—
—
—
—
-5
0.344
0.342
Max.
250
125
250
125
554
277
139
554
277
139
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.668
0.538
1.090
0.679
0.198
0.344
-0.83
-0.83
-0.87
-0.91
Min.
0.55
0.56
0.58
0.62
3.72
3.70
3.81
3.87
—
—
—
—
—
—
—
—
—
—
—
—
-4
0.368
0.364
Max.
208
104
208
104
462
231
462
231
116
116
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UI
ns
ns
UI
ns
ns
UI
UI
9
9
9
9