5CSEBA5U23C8N Altera Corporation, 5CSEBA5U23C8N Datasheet - Page 29

• Manufacturer Part Number: 5CSEBA5U23C8N
• Description: FPGA - Field Programmable Gate Array FPGA - Cyclone V SE SOC 3207 LABs 145 IO
• Manufacturer: Altera Corporation
• Series: Cyclone V SoC SEr

Specifications of 5CSEBA5U23C8N

• Rohs: yes
• Number Of Logic Blocks: 3207
• Embedded Block Ram - Ebr: 480 kbit
• Number Of I/os: 145
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.8 V, 2.5 V, 3 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UBGA-672
• Distributed Ram: 3970 kbit
• Minimum Operating Temperature: 0 C

CV-51001
2012.12.28
Cyclone V Device Overview
November 2012
July 2012
June 2012
February 2012
November 2011
October 2011
Date
2012.11.19
Version
2.1
2.0
1.2
1.1
1.0
Added support for PCIe Gen2 x4 lane configuration (PCIe-compatible)
Initial release.
Added new MBGA packages and additional U484 packages for
Cyclone V E, GX, and GT.
Added ordering code for five-transceiver devices for Cyclone V GT
and ST.
Updated the vertical migration table to add MBGA packages.
Added performance information for HPS memory controller.
Removed DDR3U support.
Updated Cyclone V ST speed grade information.
Added information on maximum transceiver channel usage restrictions
for PCI Gen2 and CPRI at 4.9152 Gbps transmit jitter compliance.
Added note on the differences between GPIO reported in Overview
with User I/O numbers shown in the Quartus II software.
Updated template.
Restructured the document.
Added the “Embedded Memory Capacity” and “Embedded Memory
Configurations” sections.
Added Table 1, Table 3, Table 16, Table 19, and Table 20.
Updated Table 2, Table 4, Table 5, Table 6, Table 7, Table 8, Table 9,
Table 10, Table 11, Table 12, Table 13, Table 14, Table 17, and Table
18.
Updated Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, and
Figure 10.
Updated the “FPGA Configuration and Processor Booting” and
“Hardware and Software Development” sections.
Text edits throughout the document.
Updated Table 1–2, Table 1–3, and Table 1–6.
Updated “Cyclone V Family Plan” on page 1–4 and “Clock Networks
and PLL Clock Sources” on page 1–15.
Updated Figure 1–1 and Figure 1–6.
Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–5, and
Table 1–6.
Updated Figure 1–4, Figure 1–5, Figure 1–6, Figure 1–7, and Figure
1–8.
Updated “System Peripherals” on page 1–18, “HPS–FPGA AXI Bridges”
on page 1–19, “HPS SDRAM Controller Subsystem” on page 1–19,
“FPGA Configuration and Processor Booting” on page 1–19, and
“Hardware and Software Development” on page 1–20.
Minor text edits.
Changes
Cyclone V Device Overview
Altera Corporation
29