5CGTFD5C5U19I7N Altera Corporation, 5CGTFD5C5U19I7N Datasheet - Page 27

• Manufacturer Part Number: 5CGTFD5C5U19I7N
• Description: FPGA - Field Programmable Gate Array FPGA - Cyclone V GT 2908 LABs 224 IOs
• Manufacturer: Altera Corporation
• Series: Cyclone V GTr

Specifications of 5CGTFD5C5U19I7N

• Rohs: yes
• Number Of Logic Blocks: 2908
• Embedded Block Ram - Ebr: 4884 kbit
• Number Of I/os: 224
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.1 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-484
• Distributed Ram: 424 kbit
• Minimum Operating Temperature: - 40 C

CV-51001
2012.12.28
Cyclone V Device Overview
Dynamic and Partial Reconfiguration
Dynamic Reconfiguration
Partial Reconfiguration
Enhanced Configuration and Configuration via Protocol
Table 24: Configuration Modes and Features Supported by Cyclone V Devices
AS through the EPCS
and EPCQ serial
configuration device
PS through CPLD or
external
microcontroller
FPP
The Cyclone V devices support dynamic reconfiguration and partial reconfiguration.
The dynamic reconfiguration feature allows you to dynamically change the transceiver data rates, PMA
settings, or protocols of a channel, without affecting data transfer on adjacent channels. This feature is ideal
for applications that require on-the-fly multiprotocol or multirate support. You can reconfigure the PMA
and PCS blocks with dynamic reconfiguration.
Partial reconfiguration allows you to reconfigure part of the device while other sections of the device remain
operational. This capability is important in systems with critical uptime requirements because it allows you
to make updates or adjust functionality without disrupting services.
Apart from lowering cost and power consumption, partial reconfiguration increases the effective logic density
of the device because placing device functions that do not operate simultaneously is not necessary. Instead,
you can store these functions in external memory and load them whenever the functions are required. This
capability reduces the size of the device because it allows multiple applications on a single device—saving
the board space and reducing the power consumption.
Altera simplifies the time-intensive task of partial reconfiguration by building this capability on top of the
proven incremental compile and design flow in the Quartus II design software. With the Altera
you do not need to know all the intricate device architecture details to perform a partial reconfiguration.
Partial reconfiguration is supported through the FPP x16 configuration interface. You can seamlessly use
partial reconfiguration in tandem with dynamic reconfiguration to enable simultaneous partial reconfiguration
of both the device core and transceivers.
Cyclone V devices support 1.8 V, 2.5 V, 3.0 V, and 3.3 V programming voltages and several configuration
modes.
Mode
1 bit, 4
16 bits
Width
8 bits
Data
1 bit
bits
Max Clock
(MHz)
Rate
100
125
125
125
Max Data
(Mbps)
Rate
125
—
—
—
Decompres-
sion
Yes
Yes
Yes
Yes
Design Se-
curity
Yes
Yes
Yes
Yes
Cyclone V Device Overview
Partial Recon-
figuration
Yes
—
—
—
Altera Corporation
Parallel flash
Remote Sys-
tem Update
®
loader
solution,
Yes
—
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