LCMXO2-4000HE-4MG184C Lattice, LCMXO2-4000HE-4MG184C Datasheet - Page 21
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LCMXO2-4000HE-4MG184C
Manufacturer Part Number
LCMXO2-4000HE-4MG184C
Description
FPGA - Field Programmable Gate Array 4320 LUTs, 151 I/O 1.2V, -4 Speed, COM
Manufacturer
Lattice
Series
MachXO2r
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-4000HE-4MG184C
Rohs
yes
Number Of Logic Blocks
4320
Embedded Block Ram - Ebr
92 Kbit
Number Of I/os
150
Maximum Operating Frequency
269 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
BGA-184
Distributed Ram
34 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
124 uA
User Flash Memory - Ufm
96 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-4000HE-4MG184C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling
edge the registered D1 input is registered into the register Q1. A multiplexer running off the same clock is used to
switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.
Figure 2-14 shows the output register block on the left, top and bottom edges.
Figure 2-14. MachXO2 Output Register Block Diagram (PIO on the Left, Top and Bottom Edges)
Right Edge
The output register block on the right edge is a superset of the output register on left, top and bottom edges of the
device. In addition to supporting SDR and Generic DDR modes, the output register blocks for PIOs on the right
edge include additional logic to support DDR-memory interfaces. Operation of this block is similar to that of the out-
put register block on other edges.
In DDR memory mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling
edge the registered D1 input is registered into the register Q1. A multiplexer running off the DQSW90 signal is used
to switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.
Figure 2-15 shows the output register block on the right edge.
SCLK
TD
D0
D1
D
Q
D/L Q
D
D/L Q
Q
2-17
Q0
Q1
MachXO2 Family Data Sheet
Tri-state path
Output path
TQ
Q
Architecture