LCMXO2-4000HE-4MG184C Lattice, LCMXO2-4000HE-4MG184C Datasheet - Page 64
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LCMXO2-4000HE-4MG184C
Manufacturer Part Number
LCMXO2-4000HE-4MG184C
Description
FPGA - Field Programmable Gate Array 4320 LUTs, 151 I/O 1.2V, -4 Speed, COM
Manufacturer
Lattice
Series
MachXO2r
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-4000HE-4MG184C
Rohs
yes
Number Of Logic Blocks
4320
Embedded Block Ram - Ebr
92 Kbit
Number Of I/os
150
Maximum Operating Frequency
269 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
BGA-184
Distributed Ram
34 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
124 uA
User Flash Memory - Ufm
96 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-4000HE-4MG184C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
t
t
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Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Aligned
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t
f
f
Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Centered
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t
f
f
Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Aligned
t
t
f
f
f
Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Centered
t
t
f
f
f
Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input - GDDRX4_RX.ECLK.Aligned
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f
f
f
HPLL
SU_DELPLL
H_DELPLL
DVA
DVE
DATA
DDRX1
SU
HO
DATA
DDRX1
DVA
DVE
DATA
DDRX2
SCLK
SU
HO
DATA
DDRX2
SCLK
DVA
DVE
DATA
DDRX4
SCLK
Parameter
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO
Input Register with Data Input
Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Input Data Valid After CLK
Input Data Hold After CLK
DDRX1 Input Data Speed
DDRX1 SCLK Frequency
Input Data Setup Before CLK
Input Data Hold After CLK
DDRX1 Input Data Speed
DDRX1 SCLK Frequency
Input Data Valid After CLK
Input Data Hold After CLK
DDRX2 Serial Input Data
Speed
DDRX2 ECLK Frequency
SCLK Frequency
Input Data Setup Before CLK
Input Data Hold After CLK
DDRX2 Serial Input Data
Speed
DDRX2 ECLK Frequency
SCLK Frequency
Input Data Valid After ECLK
Input Data Hold After ECLK
DDRX4 Serial Input Data
Speed
DDRX4 ECLK Frequency
SCLK Frequency
Description
MachXO2-1200ZE
MachXO2-2000ZE
MachXO2-4000ZE
MachXO2-7000ZE
MachXO2-1200ZE
MachXO2-2000ZE
MachXO2-4000ZE
MachXO2-7000ZE
MachXO2-1200ZE
MachXO2-2000ZE
MachXO2-4000ZE
MachXO2-7000ZE
All MachXO2
devices, all sides
All MachXO2
devices, all sides
MachXO2-640U,
MachXO2-1200/U
and larger devices,
bottom side only
MachXO2-640U,
MachXO2-1200/U
and larger devices,
bottom side only
MachXO2-640U,
MachXO2-1200/U
and larger devices,
bottom side only
Device
3-25
0.670
1.319
0.717
0.602
0.472
0.363
0.662
-1.36
-1.35
-1.43
-1.41
Min.
0.66
0.68
0.68
0.73
5.14
5.11
5.27
5.15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-3
DC and Switching Characteristics
0.382
0.361
0.307
Max.
140
140
280
140
280
140
420
210
—
—
—
—
—
—
—
—
—
—
—
—
—
70
—
—
70
—
70
—
—
70
—
53
MachXO2 Family Data Sheet
0.684
1.412
1.010
0.625
0.672
0.501
0.650
-1.36
-1.35
-1.43
-1.41
Min.
0.68
0.70
0.71
0.74
5.69
5.67
5.84
5.71
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-2
0.401
0.346
0.316
Max.
116
116
234
117
234
117
352
176
58
58
59
59
44
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.693
1.462
1.340
0.648
0.865
0.743
0.649
-1.36
-1.35
-1.43
-1.41
Min.
0.80
0.83
0.84
0.87
6.20
6.17
6.35
6.23
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-1
0.417
0.334
0.326
Max.
194
194
292
146
98
49
98
49
97
49
97
49
37
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UI
UI
UI
UI
UI
UI
9
9
9
9
9