LCMXO2-256ZE-1SG32I Lattice, LCMXO2-256ZE-1SG32I Datasheet - Page 29
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LCMXO2-256ZE-1SG32I
Manufacturer Part Number
LCMXO2-256ZE-1SG32I
Description
FPGA - Field Programmable Gate Array 256 LUTs 22 I/O 1.2V -1 Speed
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-256ZE-1SG32I
Rohs
yes
Number Of Gates
256
Embedded Block Ram - Ebr
0 Kbit
Number Of I/os
22
Maximum Operating Frequency
104 MHz
Operating Supply Voltage
1.14 V to 1.26 V
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
Package / Case
QFN-32
Distributed Ram
2 Kbit
Operating Supply Current
18 uA
Factory Pack Quantity
490
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Table 2-13. Supported Output Standards
sysIO Buffer Banks
The numbers of banks vary between the devices of this family. MachXO2-1200U, MachXO2-2000/U and higher
density devices have six I/O banks (one bank on the top, right and bottom side and three banks on the left side).
The MachXO2-1200 and lower density devices have four banks (one bank per side). Figures 2-18 and 2-19 show
the sysIO banks and their associated supplies for all devices.
Single-Ended Interfaces
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
LVCMOS33, Open Drain
LVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
SSTL25 (Class I)
SSTL18 (Class I)
HSTL18(Class I)
Differential Interfaces
LVDS
BLVDS, MLVDS, RSDS
LVPECL
Differential SSTL18
Differential SSTL25
Differential HSTL18
1. MachXO2-640U, MachXO2-1200/U and larger devices have dedicated LVDS buffers.
2. These interfaces can be emulated with external resistors in all devices.
1, 2
2
Output Standard
2
2-25
V
CCIO
2.5, 3.3
3.3
3.3
2.5
1.8
1.5
1.2
3.3
2.5
1.8
1.8
2.5
3.3
1.8
2.5
1.8
—
—
—
—
—
(Typ.)
MachXO2 Family Data Sheet
Architecture
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