5CSEBA6U19C8N Altera Corporation, 5CSEBA6U19C8N Datasheet - Page 2

• Manufacturer Part Number: 5CSEBA6U19C8N
• Description: FPGA - Field Programmable Gate Array FPGA - Cyclone V SE SOC 4150 LABs 66 IOs
• Manufacturer: Altera Corporation
• Series: Cyclone V SoC SEr

Specifications of 5CSEBA6U19C8N

• Rohs: yes
• Number Of Logic Blocks: 4150
• Embedded Block Ram - Ebr: 621 kbit
• Number Of I/os: 66
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.8 V, 2.5 V, 3 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UBGA-484
• Distributed Ram: 5140 kbit
• Minimum Operating Temperature: 0 C

Altera Corporation
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Summary of Cyclone V Features
Table 2: Summary of Features for Cyclone V Devices
Embedded Hard IP
Phase-locked loops
High-performance
Internal memory
General-purpose
high-speed serial
Clock networks
I/Os (GPIOs)
Cyclone V Device Overview
FPGA fabric
Technology
Low-power
Packaging
interface
Feature
(PLLs)
blocks
blocks
FPGA
Memory controller
Embedded
transceiver I/O
Enhanced 8-input ALM with four registers
Variable-precision
DSP
TSMC's 28-nm low-power (28LP) process technology
1.1 V core voltage
Wirebond low-halogen packages
Multiple device densities with compatible package footprints for seamless migration
between different device densities
RoHS-compliant options
M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)
Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can
use up to 25% of the ALMs as MLAB memory
Up to 550 MHz global clock network
Global, quadrant, and peripheral clock networks
Clock networks that are not used can be powered down to reduce dynamic power
Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)
Integer mode and fractional mode
875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter
400 MHz/800 Mbps external memory interface
On-chip termination (OCT)
3.3 V support with up to 16 mA drive strength
614 Mbps to 5.0 Gbps integrated transceiver speed
Transmit pre-emphasis and receiver equalization
Dynamic partial reconfiguration of individual channels
DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support
PCI Express
multifunction support, endpoint, and root port
Native support for up to three signal processing precision levels
(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same
variable-precision DSP block
64-bit accumulator and cascade
Embedded internal coefficient memory
Preadder/subtractor for improved efficiency
®
(PCIe
Description
®
) Gen2 and Gen1 (x1, x2, or x4) hard IP with
Cyclone V Device Overview
2012.12.28
CV-51001