5CSEBA6U19C8N Altera Corporation, 5CSEBA6U19C8N Datasheet - Page 24

• Manufacturer Part Number: 5CSEBA6U19C8N
• Description: FPGA - Field Programmable Gate Array FPGA - Cyclone V SE SOC 4150 LABs 66 IOs
• Manufacturer: Altera Corporation
• Series: Cyclone V SoC SEr

Specifications of 5CSEBA6U19C8N

• Rohs: yes
• Number Of Logic Blocks: 4150
• Embedded Block Ram - Ebr: 621 kbit
• Number Of I/os: 66
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.8 V, 2.5 V, 3 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UBGA-484
• Distributed Ram: 5140 kbit
• Minimum Operating Temperature: 0 C

Altera Corporation
24
SoC FPGA with HPS
HPS Features
22
23
24
25
SDI, SD/HD, and
3G-SDI
JESD204A
Serial ATA Gen1 and
Gen2
CPRI 4.1
OBSAI RP3
V-by-One HS
DisplayPort 1.2
The 0.27-Gbps data rate is supported using oversampling user logic that you must implement in the FPGA
fabric.
The 0.3125-Gbps data rate is supported using oversampling user logic that you must implement in the FPGA
fabric.
High-voltage output mode (1000-BASE-CX) is not supported.
Pending characterization.
Each SoC FPGA combines an FPGA fabric and an HPS in a single device. This combination delivers the
flexibility of programmable logic with the power and cost savings of hard IP in these ways:
The HPS consists of a dual-core ARM MPCore processor, a rich set of peripherals, and a shared multiport
SDRAM memory controller, as shown in the following figure.
Cyclone V Device Overview
PCS Support
Reduces board space, system power, and bill of materials cost by eliminating a discrete embedded processor
Allows you to differentiate the end product in both hardware and software, and to support virtually any
interface standard
Extends the product life and revenue through in-field hardware and software updates
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25
0.768 to 3.072
0.27
1.62 and 2.7
Rates(Gbps)
0.3125
1.5 and 3.0
Up to 3.75
0.6144 to
and 2.97
4.9152
3.125
22
Data
, 1.485,
23
to
Custom PHY IP core with preset
feature
Custom PHY IP core
Transmitter Data Path Feature
Custom PHY IP core with
preset feature
Electrical idle
Dedicated deterministic
latency PHY IP core
Transmitter (TX) manual
bit-slip mode
Custom PHY IP core with preset
feature
Receiver Data Path Feature
Custom PHY IP core with
preset feature
Signal detect
Wider spread of
asynchronous SSC
Dedicated deterministic
latency PHY IP core
Receiver (RX) deterministic
latency state machine
Custom PHY IP core
Wider spread of
asynchronous SSC
Cyclone V Device Overview
2012.12.28
CV-51001