PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 38

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
The 64-bit memory write transaction is similar to the 32-bit target write transaction with additional PCI signals
required for 64-bit signaling.
Figure 2-10. 64-bit Master Single Write Transaction with a 64-bit Local Interface
lm_burst_length[11:0]
lm_termination[2:0]
lm_burst_cnt[12:0]
lm_cben_in[3:0]
lm_cben_in[7:4]
lm_64bit_transn
lm_hdata_xfern
lm_ldata_xfern
l_ad_in[63:32]
lm_status[3:0]
l_ad_in[31:0]
lm_req64n
ad[63:32]
cben[3:0]
cben[7:4]
ad[31:0]
lm_gntn
lm_rdyn
devseln
ack64n
framen
req64n
par64
irdyn
trdyn
reqn
gntn
par
clk
1
Figure 2-10
2
Termination
Bus
3
Bus Length
Don’t care
Command
Don’t care
Don’t care
Address
( = 1 )
Bus
and
4
Table 2-14
5
Don’t care
Don’t care
Don’t care
Address
Loading
38
Don’t care
Don’t care
show a basic 64-bit write transaction.
6
Don’t care
Command
Enable 1
Enable 2
Address
Data 1
Data 2
Byte
Byte
Bus
Don’t care
7
Address
Parity
Transaction
Bus Length
8
( = 1 )
Bus
Byte Enable 1
Byte Enable 2
Data 1
Data 2
Don’t care
9
Data Parity 1
Data Parity 2
Don’t care
Don’t care
Don’t care
Don’t care
10
Functional Description
Termination
Termination
PCI IP Core User’s Guide
11
Normal
Bus
0
12