LCMXO2-1200ZE-1UWG25ITR50 Lattice, LCMXO2-1200ZE-1UWG25ITR50 Datasheet - Page 23

• Manufacturer Part Number: LCMXO2-1200ZE-1UWG25ITR50
• Description: FPGA - Field Programmable Gate Array 19 LUTs 19 IO 1.2V 1 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-1200ZE-1UWG25ITR50

• Rohs: yes
• Number Of Gates: 1200
• Embedded Block Ram - Ebr: 64 Kbit
• Number Of I/os: 19
• Maximum Operating Frequency: 400 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Package / Case: WLCPS-25
• Distributed Ram: 10 Kbit
• Operating Supply Current: 56 uA

These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by
the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment
based on the control signals UPDATE and SEL0 from the control block. The third stage pipeline registers pass the
data to the device core synchronized to the low-speed system clock. Figure 2-16 shows a block diagram of the
input gearbox.
Figure 2-16. Input Gearbox
D
ECLK0/1
UPDATE
SEL0
Q21
Q43
Q65
Q_6
Q32
Q54
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
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Q0_
Q21
Q43
Q65
Q_6
Q54
Q32
Q10
Q10
Q32
Q54
Q_6
Q21
Q43
Q65
2-19
CE
D Q
CE
CE
CE
CE
CE
CE
CE
D Q
D Q
D Q
D Q
D Q
D Q
D Q
cdn
S1
S0
S2
S4
S6
S7
S5
S3
D Q
D Q
D Q
D Q
D Q
MachXO2 Family Data Sheet
D
D
D
T0
T2
T4
T6
T5
T3
T1
T7
Q0
Q2
Q4
Q6
Q7
Q5
Q3
Q1
SCLK
Architecture