LCMXO2-1200ZE-1UWG25ITR50 Lattice, LCMXO2-1200ZE-1UWG25ITR50 Datasheet - Page 78

• Manufacturer Part Number: LCMXO2-1200ZE-1UWG25ITR50
• Description: FPGA - Field Programmable Gate Array 19 LUTs 19 IO 1.2V 1 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-1200ZE-1UWG25ITR50

• Rohs: yes
• Number Of Gates: 1200
• Embedded Block Ram - Ebr: 64 Kbit
• Number Of I/os: 19
• Maximum Operating Frequency: 400 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Package / Case: WLCPS-25
• Distributed Ram: 10 Kbit
• Operating Supply Current: 56 uA

General Purpose
DONE
MCLK/CCLK
SN
CSSPIN
SI/SISPI
SO/SPISO
SCL
SDA
Signal Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Open Drain pin. Indicates that the configuration sequence is complete, and the start-up
sequence is in progress.
Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Configuration
Clock for configuring an FPGA in SPI and SPIm configuration modes.
Slave SPI active low chip select input.
Master SPI active low chip select output.
Slave SPI serial data input and master SPI serial data output.
Slave SPI serial data output and master SPI serial data input.
Slave I
Slave I
2
2
C clock input and master I
C data input and master I
4-2
2
2
C data output.
C clock output.
Descriptions
MachXO2 Family Data Sheet
Pinout Information