LFE2-6E-6T144I Lattice, LFE2-6E-6T144I Datasheet - Page 37
LFE2-6E-6T144I
Manufacturer Part Number
LFE2-6E-6T144I
Description
FPGA - Field Programmable Gate Array 6K LUTs 90 I/O DSP 1.2V -6 I
Manufacturer
Lattice
Datasheet
1.LFE2-70E-7F900C.pdf
(104 pages)
Specifications of LFE2-6E-6T144I
Number Of I/os
90
Maximum Operating Frequency
357 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
Package / Case
TQFP-144
Minimum Operating Temperature
- 40 C
Factory Pack Quantity
300
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-6E-6T144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 2-31. DQS Routing for the Bottom Edge of the Device
DLL Calibrated DQS Delay Block
Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at
the input register. For most interfaces a PLL is used for this adjustment. However in DDR memories the clock
(referred to as DQS) is not free-running so this approach cannot be used. The DQS Delay block provides the
required clock alignment for DDR memory interfaces.
The DQS signal (selected PIOs only, as shown in Figure 2-32) feeds from the PAD through a DQS delay element to
a dedicated DQS routing resource. The DQS signal also feeds polarity control logic which controls the polarity of
the clock to the sync registers in the input register blocks. Figure 2-32 and Figure 2-33 show how the DQS transi-
tion signals are routed to the PIOs.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration
(6-bit bus) signals from two dedicated DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates
DQS delays in its half of the device as shown in Figure 2-32. The DLL loop is compensated for temperature, volt-
age and process variations by the system clock and feedback loop.
DQS
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
2-34
Buffer
Delay
sysIO
LatticeECP2 Family Data Sheet
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
DQS Pin
PADA "T"
PADB "C"
Assigned
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
Architecture
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