ICE40LP1K-CB121 Lattice, ICE40LP1K-CB121 Datasheet - Page 8

• Manufacturer Part Number: ICE40LP1K-CB121
• Description: FPGA - Field Programmable Gate Array iCE40LP Ultra Low Power 1280 LUTs 1.2V
• Manufacturer: Lattice

Specifications of ICE40LP1K-CB121

• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 95
• Maximum Operating Frequency: 533 MHz
• Operating Supply Voltage: 1.14 V to 3.47 V
• Mounting Style: SMD/SMT
• Package / Case: BGA-121
• Distributed Ram: 64 Kbit
• Factory Pack Quantity: 490

iCE40 LP Series Ultra-Low Power Family
Lattice Semiconductor Corporation
www.latticesemi.com
Write Setup/Hold Time
t
t
Read Clock-Output-Time
t
t
Write and Read Clock Characteristics
t
t
t
F
SUWD
HDWD
CKORD
GBCKRM
RMWCKH
RMWCKL
RMWCYC
RAM4K Block
WMAX
Table 10
WCLK
input
GBIN
input
RCLK
input
GBIN
input
clock
RCLK
provides timing information for the logic in a RAM4K block, which includes the paths shown in
PIO
output
GBIN
RCLK
WCLK
input
input
clock
input
RCLK
PIO
PIO
GBIN
PAD
Minimum write data setup time on PIO inputs before active clock
edge on GBIN input, include interconnect delay.
Minimum write data hold time on PIO inputs after active clock edge
on GBIN input, including interconnect delay.
Clock-to-output delay from RCLK input pin, through RAM4K RDATA
output flip-flop to PIO output pad, including interconnect delay.
Global Buffer Input (GBIN) delay, though Global Buffer (GBUF)
clock network to the RCLK clock input.
Write clock High time
Write clock Low time
Write clock cycle time
Sustained write clock frequency
GBUF
PIO
Table 10:
WDATA
WCLK
Figure 9:
Typical RAM4K Block Timing
Description
RAM4K Timing Circuit
RAM Block
(256x16)
RAM4K
RDATA
RCLK
Nominal VCC
GBUF
PIO
GBIN
PAD
1.2 V
(1.32, 03-OCT-2012)
Typ.
0.62
0.42
0.48
0.98
256
5.6
2.0
0
Figure
MHz
ns
ns
ns
ns
ns
ns
ns
9.
8