iCE40LP1K-CM49TR Lattice, iCE40LP1K-CM49TR Datasheet
iCE40LP1K-CM49TR
Specifications of iCE40LP1K-CM49TR
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iCE40LP1K-CM49TR Summary of contents
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LP/HX Family Data Sheet DS1040 Version 02.2, April 2013 ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... SPI Flash or be configured by an external master such as a CPU. Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40 family of devices. Popular logic synthesis tools provide synthesis library support for iCE40. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the iCE40 device ...
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... Nonvolatile Configuration Memory (NVCM). © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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PLB Blocks The core of the iCE40 device consists of Programmable Logic Blocks (PLB) which can be programmed to perform logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in Figure 2-2. Each LC ...
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Routing There are many resources provided in the iCE40 devices to route signals individually with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PLB connections are made with three different types ...
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Global Reset Control The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 device. The global reset signal is automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For PLB ...
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Table 2-3. PLL Signal Descriptions Signal Name Direction REFERENCECLK Input BYPASS Input EXTFEEDBACK Input DYNAMICDELAY[3:0] Input LATCHINPUTVALUE Input PLLOUTGLOBAL Output PLLOUTCORE Output LOCK Output RESET Input sysMEM Embedded Block RAM Memory Larger iCE40 device includes multiple high-speed synchronous sysMEM Embedded ...
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RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized ...
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Buffer Banks iCE40 devices have up to four I/O banks with independent Vccio rails with an additional configuration bank V for the SPI I/Os. Programmable I/O (PIO) The programmable logic associated with an I/O is called a PIO. The ...
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Figure 2-6. iCE I/O Register Block Diagram CLOCK_ENABLE OUTPUT_CLK INPUT_CLK LATCH_INPUT_VALUE D_OUT_1 D_OUT_0 OUTPUT_ENABLE LATCH_INPUT_VALUE D_OUT_1 D_OUT_0 OUTPUT_ENABLE Table 2-6. PIO Signal List Pin Name OUTPUT_CLK CLOCK_ENABLE INPUT_CLK OUTPUT_ENABLE D_OUT_0/1 D_IN_0/1 LATCH_INPUT_VALUE sysIO Buffer Each I/O is associated with a ...
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Typical I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when V the level defined in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. After the POR signal is deactivated, the ...
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Power On Reset iCE40 devices have power-on reset circuitry to monitor V power-up and operation. At power-up, the POR circuitry monitors V configuration) voltage levels. It then triggers download from the on-chip NVCM or external Flash memory after reaching the ...
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... PLLs pins. CCPLL CC © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com ...
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Power Supply Ramp Rates Symbol Parameter Power supply ramp rates for all t RAMP power supplies. 1. Assumes monotonic ramp rates. 2. iCE40LP384 status is Advanced, iCE40LP4K/iCE40LP8K status is Preliminary. Power-On-Reset Voltage Levels Symbol Power-On-Reset ramp-up trip point (circuit monitoring ...
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... Frequency = 0 MHz 25°C, power supplies at nominal voltage Does not include pull-up tied to V internally in packages without PLLs pins. CCPLL Parameter iCE40LP384 iCE40LP1K iCE40LP4K iCE40LP8K All devices All devices 4 All devices = 2.5V Parameter iCE40HX1K iCE40HX4K iCE40HX8K All devices ...
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... V , used only for fast production programming, must be left floating or unconnected in applications, except CM36 and CM49 pack- PP_FAST ages MUST have the V ball connected to V PP_FAST Parameter iCE40LP384 iCE40LP1K iCE40LP4K iCE40LP8K All devices All devices All devices 5 All devices or GND and all outputs are tri-stated. ...
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... Bank Power Supply ball externally. CCIO_0 3-5 DC and Switching Characteristics iCE40 LP/HX Family Data Sheet Device Max iCE40LP1K 6.4 iCE40LP4K 15.7 iCE40LP8K 15.7 iCE40LP1K 1.5 iCE40LP4K 8.0 iCE40LP8K 8.0 iCE40LP1K 7.7 iCE40LP4K 4.2 iCE40LP8K 4.2 iCE40LP1K 8.1 iCE40LP4K 8.8 iCE40LP8K 8.8 iCE40LP1K 3.3 iCE40LP4K 8.2 iCE40LP8K 8.2 Units ...
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Peak Startup Supply Current – Preliminary – HX Devices Symbol I CCPEAK 1 I CCPLLPEAK I PP_2V5PEAK 2 I PP_FASTPEAK CCIOPEAK CC_SPIPEAK tied to V internally in packages without PLLs pins. CCPLL CC 2. ...
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Recommended Operating Conditions Standard LVCMOS 3.3 LVCMOS 2.5 LVCMOS 1.8 1 LVDS25E 1 subLVDSE 1. Inputs on-chip. Outputs are implemented with the addition of external resistors. sysIO Single-Ended DC Electrical Characteristics Input Output Standard Min. (V) Max. ...
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LVDS25E Emulation iCE40 devices can support LVDSE outputs via emulation on all banks. The output is emulated using complemen- tary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in Figure 3-1 is ...
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SubLVDS Emulation The iCE40 family supports the differential subLVDS standard. The output standard is emulated using complemen- tary LVCMOS outputs in conjunction with resistors across the driver outputs on all banks of the devices. The sub- LVDS input standard is ...
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Typical Building Block Function Performance – LP Devices Pin-to-Pin Performance (LVCMOS25) Function Basic Functions 16-bit decoder 4:1 MUX 16:1 MUX Register-to-Register Performance Function Basic Functions 16:1 MUX 16-bit adder 16-bit counter 64-bit counter Embedded Memory Functions 256x16 Pseudo-Dual Port RAM ...
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... Derating Logic Timing Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case num- bers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing num- bers at a particular temperature and voltage. ...
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... CCIO LVCMOS 2.5V CCIO LVCMOS 1.8V CCIO Over Recommended Operating Conditions Description All iCE40LP devices iCE40LP384 iCE40LP1K iCE40LP4K iCE40LP8K All iCE40LP devices iCE40LP384 iCE40LP1K iCE40LP4K iCE40LP8K iCE40LP384 iCE40LP1K iCE40LP4K iCE40LP8K 3-12 DC and Switching Characteristics iCE40 LP/HX Family Data Sheet Timing 0.13 1.03 0.16 0.00 0.23 0.00 1.76 0.17 0.00 1. Device Min ...
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... Clock to Data Hold - PIO Input Register HPLL Over Recommended Operating Conditions Description iCE40LP384 iCE40LP1K iCE40LP4K iCE40LP8K iCE40LP384 iCE40LP1K iCE40LP4K iCE40LP8K iCE40LP1K iCE40LP4K iCE40LP8K iCE40LP1K iCE40LP4K iCE40LP8K iCE40LP1K iCE40LP4K iCE40LP8K 3-13 DC and Switching Characteristics iCE40 LP/HX Family Data Sheet Device Min. Max. — -0.33 — -0.63 — -0.63 — — ...
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External Switching Characteristics – LP Devices (Continued) Parameter 4, 6 Generic DDR Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using Global Pin for Clock Input – 3 GDDRX1_RX.SCLK.Aligned t Input Data Valid After CLK DVA t ...
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External Switching Characteristics – Preliminary – HX Devices Parameter Clocks Primary Clocks f Frequency for Global Buffer Clock network All iCE40HX devices MAX_GBUF t Clock Pulse Width for Global Buffer W_GBUF t Global Buffer Clock Skew Within a Device ...
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External Switching Characteristics – Preliminary – HX Devices (Con tinued) Parameter 4, 6 Generic DDR Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using Global Pin for Clock Input – 5 GDDRX1_RX.SCLK.Aligned t Input ...
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Figure 3-3. Receiver RX.CLK.Aligned Input Waveforms RX CLK Input RX Data Input RX.Aligned Figure 3-4. Transmitter TX.CLK.Aligned Waveforms TX CLK Output TX Data Output TX.Aligned Figure 3-5. Receiver GDDR71_RX. Waveforms CLK Data 0 (4-6 bits) t DVA t DVE Figure ...
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PLL Timing – Preliminary Parameter Descriptions Input Clock Frequency f IN (REFERENCECLK, EXTFEEDBACK) f Output Clock Frequency (PLLOUT) OUT f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics t Output Clock Duty Cycle DT t ...
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SPI Master or NVCM Configuration Time Symbol Parameter POR/CRESET_B to t CONFIG Device I/O Active 1. Assumes sysMEM Block is initialized to an all zero pattern if they are used. 2. The NVCM download time is measured with a fast ...
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Port Timing Specifications Symbol Parameter Master SPI f MCLK clock frequency MCLK t CRESET_B high to first MCLK edge MCLK 1. iCE40LP4K/iCE40LP8K, iCE40HX1K/iCE40HX4K/iCE40HX8K status is Preliminary. 2. Does not apply for NVCM. Table 3-3. Available Oscillator Frequencies Frequency (MHz) ...
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Switching Test Conditions Figure 3-7 shows the output test load used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 3-4. Figure 3-7. Output Test Load, LVCMOS Standards Table 3-4. Test ...
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... SPI_SI SPI_SO © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com ...
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Signal Descriptions (Cont.) Signal Name VPP_FAST VPP_2V5 iCE40 LP/HX Family Data Sheet I/O Optional fast NVCM programming supply. V production programming, must be left floating or unconnected in appli- — cations, except CM36 and CM49 pack-ages MUST have the V ...
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Pin Information Summary General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Configuration Total General Purpose Single Ended I/O Differential Inputs per Bank Bank 0 Bank 1 Bank 2 Bank 3 Configuration Total Differential Inputs Dedicated ...
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Pin Information Summary, Continued iCE40-4KLP CM81 CM121 General Purpose I/O per Bank Bank Bank Bank Bank Configuration 4 4 Total General Purpose 63 93 Single Ended I/O Differential ...
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... Note: Markings are abbreviated for small packages. © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging Part Number iCE40LP384-CM36 iCE40LP384-CM36TR iCE40LP384-CM49 iCE40LP384-CM49TR iCE40LP384-CM81 iCE40LP384-CM81TR iCE40LP384-SG32 iCE40LP1K-CM36 iCE40LP1K-CM36TR iCE40LP1K-CM49 iCE40LP1K-CM49TR iCE40LP1K-CM81 iCE40LP1K-CM81TR iCE40LP1K-CB81 iCE40LP1K-CM121 iCE40LP1K-CB121 iCE40LP1K-QN84 iCE40LP4K-CM81 iCE40LP4K-CM81TR iCE40LP4K-CM121 iCE40LP4K-CM225 iCE40LP8K-CM81 iCE40LP8K-CM121 iCE40LP8K-CM225 High-Performance Industrial Grade Devices, Halogen Free (RoHS) Packaging ...
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... Schematic Symbols © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Pinout Information Ordering Information © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...