LFE2-6E-7F256C Lattice, LFE2-6E-7F256C Datasheet - Page 46

• Manufacturer Part Number: LFE2-6E-7F256C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 190 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7F256C

• Number Of I/os: 190
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-256
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 450

Lattice Semiconductor
3. Dual Boot Image Support
For more information on device configuration, please see details of additional technical documentation at the end
of this data sheet.
Software Error Detect (SED) Support
LatticeECP2 devices have dedicated logic to perform CRC checking of the bitstream and can be programmed such
that, if an error occurs, the device will reload from a known good boot image or generate an error signal and stop
configuring.
For more information on Software Error Detect support, please see details of additional technical documentation at
the end of this data sheet.
External Resistor
LatticeECP2 devices require a single external, 10K ohm +/- 1% value between the XRES pin and ground. Device
configuration will not be completed if this resistor is missing. There is no boundary scan register on the external
resistor pad.
On-Chip Oscillator
Every LatticeECP2 device has an internal CMOS oscillator which is used to derive a Master Clock for configura-
tion. The oscillator and the Master Clock run continuously and are available to user logic after configuration is com-
pleted. The default value of the Master Clock is 2.5MHz. Table 2-15 lists all the available Master Clock frequencies.
When a different Master Clock is selected during the design process, the following sequence takes place:
1. User selects a different Master Clock frequency
2. During configuration the device starts with the default (2.5MHz) Master Clock frequency
3. The clock configuration settings are contained in the early configuration bitstream
4. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received.
This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further
information on the use of this oscillator for configuration or user mode, please see details of additional technical
documentation at the end of this data sheet.
Table 2-15. Selectable Master Clock (CCLK) Frequencies During Configuration
Dual boot images are supported for applications requiring reliable remote updates of configuration data for the
system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded
remotely and stored in a separate location in the configuration storage device. Any time after the update the
LatticeECP2 can be re-booted from this new configuration file. If there is a problem such as corrupt data during
down or incorrect version number with this new boot image, the LatticeECP2 device can revert back to the orig-
inal backup configuration and try again. This all can be done without power cycling the system.
1. Default frequency.
CCLK (MHz)
10.0
2.5
4.3
5.4
6.9
8.1
9.2
1
CCLK (MHz)
2-43
13
15
20
26
30
34
41
CCLK (MHz)
130
45
51
55
60
—
—
LatticeECP2 Family Data Sheet
Architecture