LFE2-6E-7F256C Lattice, LFE2-6E-7F256C Datasheet - Page 63

• Manufacturer Part Number: LFE2-6E-7F256C
• Description: FPGA - Field Programmable Gate Array 6K LUTs 190 I/O DSP 1.2V -7
• Manufacturer: Lattice

Specifications of LFE2-6E-7F256C

• Number Of I/os: 190
• Maximum Operating Frequency: 420 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-256
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 450

Lattice Semiconductor
Figure 3-6. SPI4.2 and SFI Transmit Parameters
Figure 3-7. DDR1,DDR2, XGMII Transmit Parameters
LatticeECP2 External Switching Characteristics (Continued)
t
t
Primary
f
t
t
Secondary Clocks
f
t
Edge Clocks (ECK1 and ECK2)
f
t
t
1. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load.
2. DDR timing numbers based on SSTL25.
3. DDR2 timing numbers based on SSTL18.
4. SPI4.2 and SFI4 timing numbers based on LVDS25.
5. XGMII timing numbers based on HSTL class I.
6. Device supports DDR and DDR2 memory data rates down to 95MHz.
Timing v. A0.01
DQVBCLKXGMII
DQVACLKXGMII
MAX_PRI
W_PRI
SKEW_PRI
MAX_SEC
W_SEC
MAX_ECK
W_ECK
SKEW_ECK
Parameter
CLOCK or STROBE
(e.g. DQS in DDR)
CLK (e.g. RDCLK
in SPI-4.2)
DATA (e.g. RDAT[15:0],
RCTL in SPI-4.2)
DATA (e.g. DQ in DDR)
Data Invalid Before Strobe/Clock
Data Invalid After Strobe/Clock
Frequency for Primary Clock Tree
Clock Pulse Width for Primary Clock LFEC2-50
Primary Clock Skew Within a Device LFEC2-50
Frequency for Secondary Clock Tree LFEC2-50
Clock Pulse Width for Secondary
Clock
Frequency for Edge Clock
Clock Pulse Width for ECK
ECK Skew Within an Edge of the
Device
Description
TdibTdia
tDQVBS
Over Recommended Operating Conditions
tDQVAS
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
LFEC2-50
Device
TdibTdia
tDQVBS
3-16
Min.
—
—
—
—
—
tDQVAS
-7
Max.
—
—
—
—
—
DC and Switching Characteristics
LatticeECP2 Family Data Sheet
Min.
—
—
—
—
—
-6
Max.
—
—
—
—
—
Min.
—
—
—
—
—
-5
Max.
—
—
—
—
—
Units
MHz
MHz
MHz
ns
ns
ps
ps
ps
ns
ps