5CEFA7F27I7N Altera Corporation, 5CEFA7F27I7N Datasheet - Page 25

• Manufacturer Part Number: 5CEFA7F27I7N
• Description: FPGA - Field Programmable Gate Array FPGA - Cyclone V E 5648 LABs 336 IOs
• Manufacturer: Altera Corporation
• Series: Cyclone V Er

Specifications of 5CEFA7F27I7N

• Rohs: yes
• Number Of Logic Blocks: 5648
• Embedded Block Ram - Ebr: 7696 Kbit
• Number Of I/os: 336
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.1 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-672
• Distributed Ram: 836 kbit
• Minimum Operating Temperature: - 40 C

CV-51001
2012.12.28
Cyclone V Device Overview
System Peripherals and Debug Access Port
HPS–FPGA AXI Bridges
Figure 11: HPS with Dual-Core ARM Cortex-A9 MPCore Processor
Each Ethernet MAC, USB OTG, NAND flash controller, and SD/MMC controller module has an integrated
DMA controller. For modules without an integrated DMA controller, an additional DMA controller module
provides up to eight channels of high-bandwidth data transfers. Peripherals that communicate off-chip are
multiplexed with other peripherals at the HPS pin level. This allows you to choose which peripherals to
interface with other devices on your PCB.
The debug access port provides interfaces to industry standard JTAG debug probes and supports ARM
CoreSight debug and core traces to facilitate software development.
The HPS–FPGA bridges, which support the Advanced Microcontroller Bus Architecture (AMBA
eXtensible Interface (AXI
The HPS–FPGA AXI bridges allow masters in the FPGA fabric to communicate with slaves in the HPS logic,
and vice versa. For example, the HPS-to-FPGA AXI bridge allows you to share memories instantiated in the
FPGA-to-HPS AXI bridge—a high-performance bus supporting 32, 64, and 128 bit data widths that
allows the FPGA fabric to issue transactions to slaves in the HPS.
HPS-to-FPGA AXI bridge—a high-performance bus supporting 32, 64, and 128 bit data widths that
allows the HPS to issue transactions to slaves in the FPGA fabric.
Lightweight HPS-to-FPGA AXI bridge—a lower performance 32 bit width bus that allows the HPS to
issue transactions to slaves in the FPGA fabric. This bridge is primarily used for control and status register
(CSR) accesses to peripherals in the FPGA fabric.
(UART, Timer, I
NAND Flash
Configuration
Access Port
Controller
MAC (2x)
Controller
Controller
SD/MMC
OTG (2x)
Controller
Ethernet
(Trace)
Debug
DMA
USB
ETR
2
FPGA-to-HPS
Manager
C, Watchdog Timer, GPIO, SPI, Clock Manager, Reset Manager, Scan Manager, System Manager, and
™
FPGA
) specifications, consist of the following bridges:
Interconnect
Level 3
HPS-to-FPGA
Quad SPI Flash Controller)
Memory Management Unit
HPS-to-FPGA
32 KB Instruction Cache,
ACP
STM
32 KB Data Cache, and
Lightweight
with NEON/FPU,
ARM Cortex-A9
Peripherals
CPU0
ARM Cortex-A9 MPCore
Level 2 Cache (512 KB)
MPU Subsystem
On-Chip RAM
Boot ROM
64 KB
64 KB
SCU
FPGA Fabric
Memory Management Unit
32 KB Instruction Cache,
32 KB Data Cache, and
HPS
with NEON/FPU,
ARM Cortex-A9
CPU1
Cyclone V Device Overview
FPGA-to-HPS SDRAM
DDR SDRAM
Optional ECC
Controller
Multiport
with
Altera Corporation
®
) Advanced
25