5CEFA7F27I7N Altera Corporation, 5CEFA7F27I7N Datasheet - Page 26

• Manufacturer Part Number: 5CEFA7F27I7N
• Description: FPGA - Field Programmable Gate Array FPGA - Cyclone V E 5648 LABs 336 IOs
• Manufacturer: Altera Corporation
• Series: Cyclone V Er

Specifications of 5CEFA7F27I7N

• Rohs: yes
• Number Of Logic Blocks: 5648
• Embedded Block Ram - Ebr: 7696 Kbit
• Number Of I/os: 336
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.1 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-672
• Distributed Ram: 836 kbit
• Minimum Operating Temperature: - 40 C

Altera Corporation
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HPS SDRAM Controller Subsystem
FPGA Configuration and Processor Booting
Hardware and Software Development
FPGA fabric with one or both microprocessors in the HPS, while the FPGA-to-HPS AXI bridge allows logic
in the FPGA fabric to access the memory and peripherals in the HPS.
Each HPS–FPGA bridge also provides asynchronous clock crossing for data transferred between the FPGA
fabric and the HPS.
The HPS SDRAM controller subsystem contains a multiport SDRAM controller and DDR PHY that are
shared between the FPGA fabric (through the FPGA-to-HPS SDRAM interface), the level 2 (L2) cache, and
the level 3 (L3) system interconnect. The FPGA-to-HPS SDRAM interface supports AMBA AXI and Avalon
Memory-Mapped (Avalon-MM) interface standards, and provides up to six individual ports for access by
masters implemented in the FPGA fabric.
To maximize memory performance, the SDRAM controller subsystem supports command and data
reordering, deficit round-robin arbitration with aging, and high-priority bypass features. The SDRAM
controller subsystem supports DDR2, DDR3, or LPDDR2 devices up to 4 Gb in density operating at up to
400 MHz (800 Mbps data rate).
The FPGA fabric and HPS in the SoC FPGA are powered independently. You can reduce the clock frequencies
or gate the clocks to reduce dynamic power, or shut down the entire FPGA fabric to reduce total system
power.
You can configure the FPGA fabric and boot the HPS independently, in any order, providing you with more
design flexibility:
Note:
For hardware development, you can configure the HPS and connect your soft logic in the FPGA fabric to
the HPS interfaces using the Qsys system integration tool in the Quartus II software.
For software development, the ARM-based SoC FPGA devices inherit the rich software development
ecosystem available for the ARM Cortex-A9 MPCore processor. The software development process for
Altera SoC FPGAs follows the same steps as those for other SoC devices from other manufacturers. Support
for Linux, VxWorks
on the operating systems support availability, contact the
You can begin device-specific firmware and software development on the Altera SoC FPGA Virtual Target.
The Virtual Target is a fast PC-based functional simulation of a target development system—a model of a
complete development board that runs on a PC. The Virtual Target enables the development of device-specific
production software that can run unmodified on actual hardware.
Cyclone V Device Overview
You can boot the HPS independently. After the HPS is running, the HPS can fully or partially reconfigure
the FPGA fabric at any time under software control. The HPS can also configure other FPGAs on the
board through the FPGA configuration controller.
You can power up both the HPS and the FPGA fabric together, configure the FPGA fabric first, and then
boot the HPS from memory accessible to the FPGA fabric.
Although the FPGA fabric and HPS are on separate power domains, the HPS must remain powered
up during operation while the FPGA fabric can be powered up or down as required.
®
, and other operating systems will be available for the SoC FPGAs. For more information
Altera sales
team.
Cyclone V Device Overview
2012.12.28
CV-51001
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