KSZ8851-16MLLU Micrel, KSZ8851-16MLLU Datasheet - Page 44

• Manufacturer Part Number: KSZ8851-16MLLU
• Description: Ethernet ICs Single-Port Ethernet Controller (Automotive Grade)
• Manufacturer: Micrel

Specifications of KSZ8851-16MLLU

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

The Host MAC address is used to define the individual destination address that the KSZ8851-16MLL responds to when
receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are
received from left to right, and the bits within each byte are received from right to left (LSB to MSB). For example, the
actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101.
These three registers value for Host MAC address 01:23:45:67:89:AB will be held as below:
MARL[15:0] = 0x89AB
MARM[15:0] = 0x4567
MARH[15:0] = 0x0123
Host MAC Address Register Low (0x10 – 0x11): MARL
The following table shows the register bit fields for Low word of Host MAC address.
Host MAC Address Register Middle (0x12 – 0x13): MARM
The following table shows the register bit fields for middle word of Host MAC address.
Host MAC Address Register High (0x14 – 0x15): MARH
The following table shows the register bit fields for high word of Host MAC address.
0x16 – 0x1F: Reserved
On-Chip Bus Control Register (0x20 – 0x21): OBCR
This register controls the on-chip bus clock speed for the KSZ8851-16MLL. The default of the on-chip bus clock speed is
125MHz. When the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best
performance.
EEPROM Control Register (0x22 – 0x23): EEPCR
To support an external EEPROM, pulled-up the EED_IO pin to High; otherwise, it is pulled-down to Low. If an external
May 2012
Micrel, Inc.
Bit
15-0
Bit
15-0
Bit
15-0
Bit
15-7
6
5-3
2
1-0
Default Value
Default Value
Default Value
Default Value
0x0
0
0
-
-
-
-
-
R/W
R/W
R/W
R/W
RW
RW
RW
RW
RW
RW
RW
RW
Description
MARL MAC Address Low
The least significant word of the MAC address.
Description
MARM MAC Address Middle
The middle word of the MAC address.
Description
MARH MAC Address High
The Most significant word of the MAC address.
Description
Reserved.
Output Pin Drive Strength
Bi-directional or output pad drive strength selection.
0: 8 mA; 1: 16 mA
Reserved.
On-Chip Bus Clock Selection
0: 125MHz (default setting is divided by 1, Bit[1:0]=00)
1: NA (reserved)
On-Chip Bus Clock Divider Selection
00: Divided by 1; 01: Divided by 2; 10: Divided by 3; 11: NA (reserved).
For example to contol the bus clock speed as below:
If Bit 2 = 0 and this value is set 00 to select 125 MHz.
If Bit 2 = 0 and this value is set 01 to select 62.5 MHz.
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KSZ8851-16MLL/MLLI
M9999-050112-2.1