AT25DQ321-SH-B Adesto Technologies, AT25DQ321-SH-B Datasheet
AT25DQ321-SH-B
Specifications of AT25DQ321-SH-B
Related parts for AT25DQ321-SH-B
AT25DQ321-SH-B Summary of contents
Page 1
... Data retention: 20 years Complies with full industrial temperature range Industry standard green (Pb/Halide-free/RoHS compliant) package options 8-lead SOIC (208-mil wide) 8-pad Ultra-thin DFN ( 0.6mm) 16-lead SOIC (300-mil wide) AT25DQ321 DATASHEET 8718D–DFLASH–12/2012 ...
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... EEPROM devices. The physical sectoring and the erase block sizes of the AT25DQ321 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently ...
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... Asserted State Type Low Input - Input - Input/Output ) pin will Input/Output ) pin will 1 AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 3 ...
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... SCK NC 2 GND (I Asserted State Type ) of data to 3-0 Low Input/Output Low Input/Output ) of data to 3-0 - Power - Power 16-lead SOIC 1 16 SCK GND AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 4 ...
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... SCK Interface Control SI (I And Logic HOLD (I Note: I/O 3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands. Control and Protection Logic Y-Decoder X-Decoder AT25DQ321 [DATASHEET] I/O Buffers and Latches SRAM Data Buffer Y-Gating Flash Memory Array 5 8718D–DFLASH–12/2012 ...
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... Memory Array To provide the greatest flexibility, the memory array of the AT25DQ321 can be erased in four levels of granularity including a Full Chip Erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations. The size of the physical sectors is optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions ...
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... Device Operation The AT25DQ321 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25DQ321 via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). ...
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... Up to 100MHz 3Eh 0011 1110 Up to 100MHz F0h 1111 0000 Up to 100MHz 9Fh 1001 1111 Up to 85MHz B9h 1011 1001 Up to 100MHz ABh 1010 1011 Up to 100MHz AT25DQ321 [DATASHEET] Dummy Data Address Bytes Bytes Bytes ...
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... MSB MSB Don't Care MSB Data Byte MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 MSB 9 ...
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... MSB D D MSB Data Byte MSB MSB Data Byte MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 10 ...
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... Don't Care Data Byte 1 Data Byte MSB MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 . To RDDO MSB 11 ...
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... MSB MSB MSB MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 . To RDQO 3 Byte 5 OUT MSB 12 ...
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... PP BP 32), then the Byte/Page Program command will not be executed and the 24) to set the Write Enable Latch (WEL) bit of the “Protect Sector” on page or t time to determine if the BP PP AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 26 ...
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... Address Bits A23-A0 Data IN Byte MSB MSB Data Data IN Byte MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 14 ...
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... PP BP 32), then the Byte/Page Program command will not be executed and the pin. During the first clock 1 0 and I/O pins respectively “Protect Sector” on page 26 time to determine if the BP PP AT25DQ321 [DATASHEET] 15 8718D–DFLASH–12/2012 ...
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... Input Input Data Byte 2 Data Byte MSB MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 16 ...
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... The sequence would continue with each byte of data being input only programming a single byte 32), then the Quad-Input Byte/Page Program command will not be pin. During the first clock 3 (See “Protect Sector” on page 26 time to determine if the BP PP AT25DQ321 [DATASHEET] 17 8718D–DFLASH–12/2012 ...
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... MSB MSB MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 18 ...
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... EPE bit in the Status Register. Figure 8-7. Block Erase SCK Opcode MSB High-impedance SO . BLKE Address Bits A23- MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 time to BLKE 19 ...
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... The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-8. Chip Erase SCK Opcode MSB High-impedance time to CHPE AT25DQ321 [DATASHEET] 20 8718D–DFLASH–12/2012 ...
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... Sector operation, then the device will simply ignore the opcode and no operation will be performed. The state of the WEL bit in the Status Register, as well as the SPRL (Sector Protection Registers Locked) and SLE (Sector Lockdown Enabled) bits, will not be affected. 48) is performed while a sector is erase suspended, the suspend operation will Table 8-1 AT25DQ321 [DATASHEET] 21 8718D–DFLASH–12/2012 ...
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... Not Allowed Not Allowed Allowed Allowed Allowed Allowed Allowed Not Allowed Not Allowed Not Allowed Allowed Not Allowed Not Allowed Allowed Not Allowed Allowed Allowed Not Allowed Allowed Not Allowed Allowed Allowed Not Allowed Not Allowed AT25DQ321 [DATASHEET] 22 8718D–DFLASH–12/2012 ...
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... RDY/BSY bit or the appropriate bit in the Status Register to determine if the previously suspended program or erase operation has resumed. Figure 8-10. Program/Erase Resume SCK Opcode MSB High-impedance SO time before issuing the Program/Erase Suspend command must RES AT25DQ321 [DATASHEET] 23 8718D–DFLASH–12/2012 ...
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... WEL bit will not change. Figure 9-1. Write Enable SCK Opcode MSB High-impedance AT25DQ321 [DATASHEET] 24 8718D–DFLASH–12/2012 ...
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... WEL bit will not change. Figure 9-2. Write Disable SCK Opcode MSB High-impedance AT25DQ321 [DATASHEET] 25 8718D–DFLASH–12/2012 ...
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... Figure 9-3. Protect Sector SCK Opcode High-impedance SO description Address Bits A23- for more details). If the Sector Protection AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 26 ...
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... SCK Opcode High-impedance SO Table 9-1 for Sector Protection Register values). Every physical sector of the device Address Bits A23- AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 27 ...
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... WP pin and the sector protection status. Please refer to Register” on page 39 and Table 11-1 on page 39 for bits and 2. “Write Status Register Byte 1” on page 43 for details on the Status Register format and what values can be read AT25DQ321 [DATASHEET] for command “Read Status 28 8718D–DFLASH–12/2012 ...
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... HIGH. To perform a Global Protect/Unprotect, the Write Status Register command must be issued again after the SPRL bit has been changed from New SPRL Value AT25DQ321 [DATASHEET] 29 8718D–DFLASH–12/2012 ...
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... Therefore, if operating at clock frequencies Address Bits A23- MSB “Read Status Register” Data Byte MSB MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 30 ...
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... Global Protect and Unprotect can also be performed. Can be modified Locked in current state. Protect and Unprotect Sector commands will from ignored. Global Protect and Unprotect cannot be performed. , the SPRL bit in the Status Register CC Sector (1) n Unprotected Protected AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 31 ...
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... Sector Lockdown command will be ignored and the device will reset the WEL bit in the Status Register back to a Logical 0 and return to the idle state once the CS pin has been deasserted. 44). To issue the Sector Lockdown command, the CS pin must first be LOCK AT25DQ321 [DATASHEET addition, the WEL bit in the “Freeze Sector Lockdown 32 ...
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... Figure 10-1. Sector Lockdown SCK Opcode MSB High-impedance Address Bits A23-A0 Confirmation Byte MSB MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 33 ...
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... Figure 10-2. Freeze Sector Lockdown State SCK Opcode MSB High-impedance Address Bits A23-A0 Confirmation Byte MSB MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 34 ...
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... Address Bits A23- MSB MSB Don't Care Data Byte MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 MSB 35 ...
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... Security Register will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and should take place in a time of t Security Register. Security Register Byte Number Factory Programmed by Adesto . It is not possible to suspend the programming of the OTP OTPP . . . 126 127 AT25DQ321 [DATASHEET] 36 8718D–DFLASH–12/2012 ...
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... MSB High-impedance Address Bits A23-A0 Data In Byte MSB MSB OTPP Data In Byte MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 37 ...
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... To read the OTP Security Register, the CS pin must first be asserted and the opcode Address Bits A23- MSB MSB Don't Care Data Byte MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 D D MSB 38 ...
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... Reserved for future use. All sectors are software protected. (All Sector Protection Registers are 1 – Default) Device is not write enabled. (Default) Device is write enabled. Device is ready. Device is busy with an internal operation. AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 39 ...
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... Sector Lockdown and Freeze Sector Lockdown 1 State commands are enabled sectors are program suspended. (Default sector is program suspended sectors are erase suspended. (Default sector is erase suspended. 0 Device is ready Device is busy with an internal operation. AT25DQ321 [DATASHEET] 40 8718D–DFLASH–12/2012 ...
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... Byte/Page Program, Erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, Write Status Register, or Write Configuration Register command must have been clocked into the device. AT25DQ321 [DATASHEET] 41 8718D–DFLASH–12/2012 ...
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... Status Register Byte MSB MSB Status Register Status Register Byte 2 Byte MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 42 ...
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... High-impedance SO “Global Protect/Unprotect” on page 28 Bit 5 Bit 4 Bit 3 Global Protect/Unprotect Status Register IN Byte MSB for more details. Bit 2 Bit 1 Bit 0 X AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 X 43 ...
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... Bit 5 Bit 4 Bit 3 X RSTE SLE Status Register IN Byte MSB 11-4). Any additional data bytes that are sent to Bit 2 Bit AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 Bit ...
Page 45
... R = Readable only , the first byte of data output will not be valid. Therefore, if operating at clock frequencies (2) Type Description 0 Quad-Input/Output commands and operation disabled. R/W Quad-Input/Output commands and operation enabled. 1 (WP and HOLD disabled Reserved for future use. AT25DQ321 [DATASHEET] 45 8718D–DFLASH–12/2012 ...
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... Configuration Register Out MSB MSB and HOLD 2 WP and HOLD pins function as normal Configuration Register Out MSB AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 46 ...
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... Configuration Register MSB and the WEL bit in the Status Register will be WRCR WRCR. time to determine if WRCR Bit 2 Bit AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 While the Bit ...
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... Reset operation will be performed. Figure 12-1. Reset SCK Opcode MSB High-impedance Confirmation Byte MSB . Since the RST AT25DQ321 [DATASHEET] 48 8718D–DFLASH–12/2012 ...
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... Family Code: 100 (Quad-I/O or Rapid4 87h Density Code: 00111 (32-Mbit) Sub Code: 000 (Quad-I/O Series) 00h Product Variant: 00000 (Standard Version) Hex Value Details RFU: Reserved for Future Use 00h Density Code: 00000 (Initial Version) AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 ™ ...
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... Opcode SI 9Fh High-impedance SO Manufacturer ID Note: Each transition shown for SI and SO represents one byte (8 bits 1Fh 86h 00h Device ID Device ID Byte 1 Byte 2 String Length 01h 00h EDI EDI Data Byte 1 AT25DQ321 [DATASHEET] 50 8718D–DFLASH–12/2012 ...
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... Deep Power-Down mode. Figure 12-3. Deep Power-Down SCK Opcode MSB High-impedance SO Active Current I CC Standby Mode Current t EDPD Deep Power-down Mode Current . EDPD AT25DQ321 [DATASHEET] 51 8718D–DFLASH–12/2012 ...
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... Figure 12-4. Resume from Deep Power-Down CS 0 SCK SI 1 MSB High-impedance SO Active Current I CC Deep Power-down Mode Current t RDPD Opcode Standby Mode Current and return to the standby mode. After RDPD AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 52 ...
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... If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted and the device will reset the WEL bit in the Status Register back to the Logical 0 state. Figure 12-5. Hold Mode CS SCK HOLD Hold Hold Hold AT25DQ321 [DATASHEET] 53 8718D–DFLASH–12/2012 ...
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... V = Min -100μ Min AT25DQ321 -40C to 85C 2.7V to 3.6V Min Typ Max Units 25 50 μ μ μA 1 μ AT25DQ321 [DATASHEET] 54 8718D–DFLASH–12/2012 ...
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... MHz 85 MHz 50 MHz 85 MHz 66 MHz Min Max Units 4.3 ns 4.3 ns 0.1 V/ns 0.1 V/ 100 200 μs 1 μs 30 μs 30 μs AT25DQ321 [DATASHEET] 55 8718D–DFLASH–12/2012 ...
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... Program Erase AC Measurement Level Min Typ Max Units 1.5 3 μs 50 200 250 600 ms 400 950 25 40 sec 10 20 μ μ 200 500 μs 200 Min Max Units 70 μ 1.5 2.5 V AT25DQ321 [DATASHEET] 56 8718D–DFLASH–12/2012 ...
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... Write Status Register Byte 1 Opcode High-impedance SO t CSLH t t CLKH CLKL t DH LSB t CLKH WPH LSB of Write Status Register Data Byte t CSH t CSHH t CSHS MSB t t CLKL DIS MSB MSB of Next Opcode AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 57 ...
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... Figure 14-4. HOLD Timing – Serial Input CS SCK t HHH HOLD SI High-impedance SO Figure 14-5. HOLD Timing – Serial Output CS SCK t HHH HOLD SI t HLQZ SO t HLS t t HLH HHS t HLS t t HLH HHS t HHQX AT25DQ321 [DATASHEET] 58 8718D–DFLASH–12/2012 ...
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... Designator Product Family Device Density 32 = 32Mb Interface 1 = Serial 15.2 Green Package Options (Pb/Halide-free/RoHS-compliant) Adesto Ordering Code AT25DQ321-SH-B AT25DQ321-SH-T AT25DQ321-MH-Y AT25DQ321-MH-T AT25DQ321-S3H-B AT25DQ321-S3H-T Note: The shipping carrier option code is not marked on the devices. 8S2 8-lead, 0.208” wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 8MA1 8-pad ( ...
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... Body, Plastic Small Outline Package (EIAJ END VIEW END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE SYMBOL A 1.70 2.16 A1 0.05 0.25 b 0.35 0. 0.15 0. 5.13 5.35 E1 5.18 5. 7.70 8.26 L 0.51 0.85 q 0° 8° e 1.27 BSC 3 4/15/08 GPC DRAWING NO. STN 8S2 AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 REV ...
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... Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) C SIDE VIEW y A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM 0.45 0.55 0.60 A1 0.00 0.02 0.05 b 0.35 0.40 0.48 C 0.152 REF D 4.90 5.00 5.10 D2 3.80 4.00 4.20 E 5.90 6.00 6.10 E2 3.20 3.40 3.60 e 1.27 L 0.50 0.60 0.75 y 0.00 – 0.08 K 0.20 – – 4/15/08 GPC DRAWING NO. YFG 8MA1 AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 REV ...
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... Wide Body, Plastic Gull Wing Small Outline Package (SOIC) End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 2.35 – 2.65 0.30 A1 0.10 – 0.51 b 0.31 – D 10.30 BSC E 7.50 BSC H 10.30 BSC 1.27 L 0.40 – e 1.27 BSC C 0.20 0.33 DRAWING NO. 16S AT25DQ321 [DATASHEET] 8718D–DFLASH–12/2012 11/02/05 REV ...
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... Revision History Doc. Rev. Date 8718D 12/2012 8718C 11/2012 8718B 02/2012 8718A 04/2010 Comments Update 8S1 JEDEC SOIC to 8S2 EIAJ SOIC package option. Update to Adesto. Correct CPN. Correct electrical parameters. Update template. Initial document release. AT25DQ321 [DATASHEET] 63 8718D–DFLASH–12/2012 ...
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... Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...